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80C186XL/80C188XL
Microprocessor
User’s Manual
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80C186XL/80C188XL Microprocessor User’s Manual 1995
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Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
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CONTENTS CHAPTER 1 INTRODUCTION 1.1 HOW TO USE THIS MANUAL....................................................................................... 1-2 1.2 RELATED DOCUMENTS .............................................................................................. 1-3 1.3 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-4 1.3.1 FaxBack Service ................................................................................................
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CONTENTS 2.3 INTERRUPTS AND EXCEPTION HANDLING............................................................ 2-39 2.3.1 Interrupt/Exception Processing ...............................................................................2-39 2.3.1.1 Non-Maskable Interrupts ...............................................................................2-42 2.3.1.2 Maskable Interrupts .......................................................................................2-43 2.3.1.3 Exceptions ............
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CONTENTS CHAPTER 4 PERIPHERAL CONTROL BLOCK 4.1 PERIPHERAL CONTROL REGISTERS........................................................................ 4-1 4.2 PCB RELOCATION REGISTER.................................................................................... 4-1 4.3 RESERVED LOCATIONS ............................................................................................. 4-4 4.4 ACCESSING THE PERIPHERAL CONTROL BLOCK.................................................. 4-4 4.4.1 Bus Cyc
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CONTENTS 6.4.5 Memory or I/O Bus Cycle Decoding ........................................................................6-17 6.4.6 Programming Considerations ..................................................................................6-17 6.5 CHIP-SELECTS AND BUS HOLD............................................................................... 6-18 6.6 EXAMPLES ................................................................................................................. 6-18 6.6.1 Exa
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CONTENTS 8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT ............................................... 8-11 8.4.1 Interrupt Control Registers ......................................................................................8-12 8.4.2 Interrupt Request Register ......................................................................................8-16 8.4.3 Interrupt Mask Register ...........................................................................................8-16 8.4.4 Priority Mask
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CONTENTS 10.1.3 DMA Requests ........................................................................................................10-3 10.1.4 External Requests ...................................................................................................10-4 10.1.4.1 Source Synchronization ................................................................................10-5 10.1.4.2 Destination Synchronization ..........................................................................10-5
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CONTENTS 11.3.1.4 Transcendental Instructions ..........................................................................11-5 11.3.1.5 Constant Instructions .....................................................................................11-6 11.3.1.6 Processor Control Instructions ......................................................................11-6 11.3.2 80C187 Data Types ................................................................................................11-7 11.4 MICROPRO
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CONTENTS FIGURES Figure Page 2-1 Simplified Functional Block Diagram of the 80C186 Family CPU ................................2-2 2-2 Physical Address Generation .......................................................................................2-3 2-3 General Registers ........................................................................................................2-4 2-4 Segment Registers................................................................................................
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CONTENTS FIGURES Figure Page 3-15 Generating a Normally Not-Ready Bus Signal ...........................................................3-16 3-16 Generating a Normally Ready Bus Signal..................................................................3-17 3-17 Normally Not-Ready System Timing ..........................................................................3-18 3-18 Normally Ready System Timings ...............................................................................3-19 3-19 Typi
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CONTENTS FIGURES Figure Page 6-11 Wait State and Ready Control Functions ...................................................................6-16 6-12 Using Chip-Selects During HOLD ..............................................................................6-18 6-13 Typical System ...........................................................................................................6-19 7-1 Refresh Control Unit Block Diagram..................................................................
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CONTENTS FIGURES Figure Page 10-3 Source-Synchronized Transfers.................................................................................10-5 10-4 Destination-Synchronized Transfers ..........................................................................10-6 10-5 Two-Channel DMA Module ........................................................................................10-9 10-6 Examples of DMA Priority..................................................................................
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CONTENTS TABLES Table Page 1-1 Comparison of 80C186 Modular Core Family Products...............................................1-2 1-2 Related Documents and Software................................................................................1-3 2-1 Implicit Use of General Registers.................................................................................2-5 2-2 Logical Address Sources............................................................................................2-13 2-3 D
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CONTENTS TABLES Table Page C-1 Instruction Format Variables........................................................................................C-1 C-2 Instruction Operands ...................................................................................................C-2 C-3 Flag Bit Functions........................................................................................................C-3 C-4 Instruction Set .......................................................................
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CONTENTS EXAMPLES Example Page 5-1 Initializing the Power Management Unit for Power-Save Mode .................................5-14 6-1 Initializing the Chip-Select Unit...................................................................................6-20 7-1 Initializing the Refresh Control Unit ............................................................................7-11 8-1 Initializing the Interrupt Control Unit for Master Mode ................................................8-31 9-1 Con
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1 Introduction
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CHAPTER 1 INTRODUCTION The 8086 microprocessor was first introduced in 1978 and gained rapid support as the microcom- puter engine of choice. There are literally millions of 8086/8088-based systems in the world to- day. The amount of software written for the 8086/8088 is rivaled by no other architecture. By the early 1980’s, however, it was clear that a replacement for the 8086/8088 was necessary. An 8086/8088 system required dozens of support chips to implement even a moderately complex design.
