Streszczenie treści zawartej na stronie nr. 1
FUJITSU MICROELECTRONICS
CM71-00105-1E
CONTROLLER MANUAL
FR81 Family
32-BIT MICROCONTROLLER
PROGRAMMING MANUAL
Streszczenie treści zawartej na stronie nr. 2
Streszczenie treści zawartej na stronie nr. 3
FR81 Family 32-BIT MICROCONTROLLER PROGRAMMING MANUAL For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED
Streszczenie treści zawartej na stronie nr. 4
Streszczenie treści zawartej na stronie nr. 5
PREFACE ■ Objectives and targeted reader FR81 Family is a 32 bit single chip microcontroller with CPU of new RISC Architecture as the core. FR81 Family has specifications that are optimum for embedded use requiring high performance CPU processing power. This manual explains the programming model and execution instructions for engineers developing a product using this FR81 Family Microcontroller, especially the programmers who produce programs using assembly language of the assembler for FR/FR80
Streszczenie treści zawartej na stronie nr. 6
• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. � The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information.
Streszczenie treści zawartej na stronie nr. 7
CONTENTS CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU ............................................................ 1 1.1 Features of FR81 Family CPU ............................................................................................................ 2 1.2 Changes from the earlier FR Family ................................................................................................... 4 CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 7 2
Streszczenie treści zawartej na stronie nr. 8
CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 41 4.1 Reset ................................................................................................................................................ 42 4.2 Basic Operations in EIT Processing ................................................................................................. 43 4.2.1 Types of EIT Processing and Prior Preparation ..............................................
Streszczenie treści zawartej na stronie nr. 9
5.3.1 Occurrence of data hazard .......................................................................................................... 74 5.3.2 Register Bypassing ...................................................................................................................... 74 5.3.3 Interlocking .................................................................................................................................. 75 5.3.4 Interlocking produced by reference to R15 after Chan
Streszczenie treści zawartej na stronie nr. 10
7.15 ASR (Arithmetic shift to the Right Direction) ................................................................................... 133 7.16 ASR2 (Arithmetic shift to the Right Direction) ................................................................................. 135 7.17 BANDH (And 4bit Immediate Data to Higher 4bit of Byte Data in Memory) ................................... 137 7.18 BANDL (And 4bit Immediate Data to Lower 4bit of Byte Data in Memory) ...............................
Streszczenie treści zawartej na stronie nr. 11
7.61 EXTUB (Unsign Extend from Byte Data to Word Data) .................................................................. 225 7.62 EXTUH (Unsign Extend from Byte Data to Word Data) .................................................................. 227 7.63 FABSs (Single Precision Floating Point Absolute Value) ............................................................... 229 7.64 FADDs (Single Precision Floating Point Add) .......................................................................
Streszczenie treści zawartej na stronie nr. 12
7.108 LDI:8 (Load Immediate 8bit Data to Destination Register) ............................................................. 300 7.109 LDM0 (Load Multiple Registers) ..................................................................................................... 302 7.110 LDM1 (Load Multiple Registers) ..................................................................................................... 304 7.111 LDUB (Load Byte Data in Memory to Register) ................................
Streszczenie treści zawartej na stronie nr. 13
7.155 ST (Store Word Data in Register to Memory) ................................................................................. 390 7.156 ST (Store Word Data in Program Status Register to Memory) ....................................................... 392 7.157 STB (Store Byte Data in Register to Memory) ................................................................................ 394 7.158 STB (Store Byte Data in Register to Memory) ........................................................
Streszczenie treści zawartej na stronie nr. 14
x
Streszczenie treści zawartej na stronie nr. 15
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU This chapter describes the features of FR81 Family CPU and the changes from the earlier FR Family. 1.1 Features of FR81 Family CPU 1.2 Changes from the earlier FR Family CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 1
Streszczenie treści zawartej na stronie nr. 16
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.1 FR81 Family 1.1 Features of FR81 Family CPU FR81 Family CPU is meant for 32 bit RISC controller having proprietary FR81 architecture of Fujitsu. The FR81 architecture is optimized for microcontrollers by using the FR family instruction set and including improved floating-point, memory protection, and debug functions. ■ General-purpose Register Architecture It is load/store architecture based on 16 numbers of 32-bit General-purpose registers R0 to R15.
Streszczenie treści zawartej na stronie nr. 17
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.1 FR81 Family ■ Harvard Architecture An instruction can be executed efficiently based on Harvard Architecture where instruction bus for instruction access and data bus for data access are independent. ■ Multiplication Instruction Multiplication/division computation can be executed at the instruction level based on an in-built multiplier. 32-bit multiplication, signed or unsigned, is executed in 5 cycles. 16-bit multiplication is executed in 3 cycles. ■
Streszczenie treści zawartej na stronie nr. 18
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.2 FR81 Family 1.2 Changes from the earlier FR Family FR81 Family has partial addition and deletion of instructions and operational changes from the earlier FR Family (FR30 Family, FR60 Family etc.). ■ Instructions that cannot be used in FR81/FR80 Family Following instructions cannot be used in FR81/FR80 Family. � Coprocessor Instructions (COPOP, COPLD, COPST, COPSV) � Resource Instructions (LDRES, STRES) Undefined Instruction Exceptions and not the Copr
Streszczenie treści zawartej na stronie nr. 19
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.2 FR81 Family ■ Operation of INTE Instructions during Step Execution In FR81 Family, trap processing is initiated based on INTE instructions even during step execution based on step trace trap. In hitherto FR Family, trap processing is not initiated based on INTE instructions during step execution. For trap processing based on step trace trap and INTE instructions, see “4.6 Traps”. CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 5
Streszczenie treści zawartej na stronie nr. 20
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.2 FR81 Family 6 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
