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®
CY62146ESL MoBL
4-Mbit (256K x 16) Static RAM
mode reduces power consumption by more than 99% when
Features
deselected (CE HIGH). The input and output pins (IO through
0
IO ) are placed in a high impedance state when:
■ Very high speed: 45 ns
15
■ Deselected (CE HIGH)
■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■ Ultra low standby power ■ Outputs are disabled (OE HIGH)
❐ Typical Standby current: 1 μA
■ Both Byte High Enable and Byte Low Enable are disabled
❐ Maximum Standby current: 7
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® CY62146ESL MoBL Pin Configuration [1] Figure 1. 44-Pin TSOP II (Top View) A A 1 44 4 5 A A 2 43 6 3 A A 3 42 7 2 A 4 OE 1 41 A 5 40 BHE 0 6 39 CE BLE IO 7 38 IO 0 15 IO 8 37 IO 1 14 IO 9 36 IO 2 13 IO 10 IO 35 3 12 V 11 34 V CC SS V 12 SS 33 V CC IO 13 32 IO 4 11 IO 14 IO 5 31 10 IO IO 6 15 30 9 IO 16 29 IO 7 8 WE 17 28 NC A 17 18 27 A 8 A 16 19 26 A 9 A 15 A 20 25 10 A 14 A 21 24 11 A 13 22 23 A 12 Product Portfolio Power Dissipation Operating I , (mA) CC [2] Speed Standby, I SB2 Product
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® CY62146ESL MoBL Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage............................................ >2001V Exceeding the maximum ratings may impair the useful life of the (MIL-STD-883, Method 3015) device. These user guidelines are not tested. Latch up Current...................................................... >200 mA Storage Temperature.................................. –65°C to +150°C Operating Range Ambient Temperature
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® CY62146ESL MoBL Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 10 pF IN A V = V CC CC(typ) Output Capacitance 10 pF C OUT Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions TSOP II Unit Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, two-layer 77
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® CY62146ESL MoBL Data Retention Characteristics Over the Operating Range [3] Parameter Description Conditions Min Typ Max Unit V V for Data Retention 1.5 V DR CC I Data Retention Current CE > V – 0.2V, V = 1.5V 1 7 μA CC CC CCDR V > V – 0.2V or V < 0.2V IN CC IN [7] t Chip Deselect to Data 0ns CDR Retention Time [8] t Operation Recovery Time t ns R RC Data Retention Waveform DATA RETENTION MODE V V V > 1.5V V CC(min) CC(min) DR CC t t CDR R CE Notes 7. Tested initially and after any design or
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® CY62146ESL MoBL Switching Characteristics [9] Over the Operating Range 45 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW to Data Valid 45 ns ACE t OE LOW to Data Valid 22 ns DOE [10] t OE LOW to LOW-Z 5ns LZOE [10, 11] t OE HIGH to High-Z 18 ns HZOE [10] t CE LOW to Low-Z 10 ns LZCE [10, 11] t CE HIGH to High-Z 18 ns HZCE t CE LOW to Power Up 0 ns PU t CE HIGH to Power Down 45 ns
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® CY62146ESL MoBL Switching Waveforms [13, 14] Figure 2. Read Cycle No.1: Address Transition Controlled. t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [14, 15] Figure 3. Read Cycle No. 2: OE Controlled ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE t LZOE BHE/BLE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGHI MPEDANCE DATA VALID DATA OUT t LZCE t PU I CC V 50% CC 50% I SUPPLY SB CURRENT Notes , CE = V , BHE, BLE, or both = V . 13. The device is continuously selected. OE I
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® CY62146ESL MoBL Switching Waveforms (continued) [12, 16, 17] Figure 4. Write Cycle No 1: WE Controlled t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 18 DATA IN DATA IO t HZOE [12, 16, 17] Figure 5. Write Cycle 2: CE Controlled t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t t SD HD DATA DATA IO NOTE 18 IN t HZOE Notes 16. Data IO is high impedance if OE = V . IH 17. If CE goes HIGH simultaneously with WE = V , the output remains in a high impe
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® CY62146ESL MoBL Switching Waveforms (continued) [17] Figure 6. Write Cycle 3: WE controlled, OE LOW t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t HD t SD DATA IO NOTE 18 DATA IN t LZWE t HZWE [17] Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t HD t SD NOTE 18 DATA DATA IO IN t LZWE Document #: 001-43142 Rev. ** Page 9 of 12 [+] Feedback [+] Feedback
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® CY62146ESL MoBL Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby (I ) SB L X X H H High-Z Output Disabled Active (I ) CC L H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC LH LH L Data Out (IO –IO ); Read Active (I ) 0 7 CC IO –IO in High-Z 8 15 L H L L H Data Out (IO –IO ); ) Read Active (I 8 15 CC IO –IO in High-Z 0 7 L H H L L High-Z Output Disabled Active (I ) CC L H H H L High-Z Output Disabled Active (I ) CC L H H L H High-Z Output
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® CY62146ESL MoBL Package Diagrams Figure 8. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 001-43142 Rev. ** Page 11 of 12 [+] Feedback [+] Feedback
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® CY62146ESL MoBL Document History Page ® Document Title: CY62146ESL MoBL 4-Mbit (256K x 16) Static RAM Document Number: 001-43142 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 1875228 See ECN VKN/AESA New Data Sheet © Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does
