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CY7C68033/CY7C68034
EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller
• Integrated, industry-standard enhanced 8051
CY7C68033/CY7C68034 Silicon Features
— 48-MHz, 24-MHz, or 12-MHz CPU operation
• Certified compliant for Bus- or Self-powered USB 2.0
— Four clocks per instruction cycle
operation (TID# 40490118)
— Three counter/timers
• Single-chip, integrated USB 2.0 transceiver and smart SIE
• Ultra low power – 43 mA typical current draw in any mode — Expanded interrupt system
• Enhanced
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CY7C68033/CY7C68034 Default NAND Firmware Features quick configuration of some features to decrease design effort and increase time-to-market advantages. Because the NX2LP-Flex™ is intended for NAND Flash-based USB mass storage applications, a default Overview firmware image is included in the development kit with the following features: Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB • High (480-Mbps) or full (12-Mbps) speed USB support NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-ba
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CY7C68033/CY7C68034 Figure 1. Example DVB Block Diagram 8051 Microprocessor The 8051 microprocessor embedded in the NX2LP-Flex has 256 bytes of register RAM, an expanded interrupt system and Buttons NAND-Based three timer/counters. DVB Unit 8051 Clock Frequency NX2LP-Flex has an on-chip oscillator circuit that uses an LCD I/O CTL external 24-MHz (±100-ppm) crystal with the following charac- NX2LP- NAND Bank(s) CE[7:0] teristics: Flex D+/- I/O • Parallel resonant • Fundamental mode • 500-μW dri
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CY7C68033/CY7C68034 Table 1. Special Function Registers x8x 9x Ax Bx Cx Dx ExFx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1SP EXIF INT2CLR IOE SBUF1 2DPL0 MPAGE INT4CLR OEA 3DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7PCON 8 TCON SCON0 IE IP T2CON EICON EIE EIP 9 TMOD SBUF0 ATL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L BTL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H CTH0 RESERVED EP68FIFOFLGS TL2 DTH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F RESERVED AUTOPTRSET-UP GPIFSGLDATLNOX Buses Enumerat
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CY7C68033/CY7C68034 Figure 4. NX2LP-Flex Enumeration Sequence values stored in ROM space. The default silicon ID values should only be used for development purposes. Cypress requires designers to use their own Vendor ID for final Start-up products. A Vendor ID is obtained through registration with the USB Implementor’s Forum (USB-IF). Also, if the NX2LP-Flex is used as a mass storage class device, a unique USB serial number is required for each device in order to comply with the USB Mass Stora
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CY7C68033/CY7C68034 Table 3. INT2 USB Interrupts USB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes 1 0x500 SUDAV Setup Data Available 2 0x504 SOF Start of Frame (or microframe) 3 0x508 SUTOK Setup Token Received 4 0x50CSUSPEND USB Suspend request 5 0x510 USB RESET Bus reset 6 0x514 HISPEED Entered high speed operation 7 0x518 EP0ACK NX2LP ACK’d the CONTROL Handshake 8 0x51C Reserved 9 0x520 EP0-IN EP0-IN ready to be loaded with data 10 0x524 EP0-OUT EP0-OUT has USB data 11 0x52
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CY7C68033/CY7C68034 Table 4. Individual FIFO/GPIF Interrupt Sources Priority INT4VEC Value Source Notes 1 0x580 EP2PF Endpoint 2 Programmable Flag 2 0x584 EP4PF Endpoint 4 Programmable Flag 3 0x588 EP6PF Endpoint 6 Programmable Flag 4 0x58C EP8PF Endpoint 8 Programmable Flag 5 0x590 EP2EF Endpoint 2 Empty Flag 6 0x594 EP4EF Endpoint 4 Empty Flag 7 0x598 EP6EF Endpoint 6 Empty Flag 8 0x59C EP8EF Endpoint 8 Empty Flag 9 0x5A0 EP2FF Endpoint 2 Full Flag 10 0x5A4 EP4FF Endpoint 4 Full Flag 11 0x5A
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CY7C68033/CY7C68034 Table 5. Reset Timing Values Figure 6. Internal Code Memory Condition T RESET FFFF 7.5 kBytes Power-on Reset with crystal 5 ms USB registers and 4 kBytes Power-on Reset with external 200 μs + Clock stability time FIFO buffers clock source (RD#, WR#) E200 E1FF Powered Reset 200 μs 512 Bytes RAM Data (RD#, WR#)* E000 Wakeup Pins The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and 3FFF PLL. When WAKEUP
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CY7C68033/CY7C68034 Endpoint RAM Setup Data Buffer A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup Size data from a CONTROL transfer. • 3 × 64 bytes (Endpoints 0 and 1) Endpoint Configurations (High-speed Mode) • 8 × 512 bytes (Endpoints 2, 4, 6, 8) Endpoints 0 and 1 are the same for every configuration. Organization Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can • EP0 be either BULK or INTERRUPT. The endpoint buffers can be configured in any 1 of the 12 configurations s
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CY7C68033/CY7C68034 [2, 3] Table 6. Default Full-Speed Alternate Settings (continued) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) Default High-Speed Alternate Settings [2, 3] Table 7. Default High-Speed Alternate Settings Alternate Setting 0 1 2 3 ep0 64 64 64 64 [4] ep1out 0 512 bulk 64 int 64 int [4] ep1in 0 512 bulk 64 int 64 int ep2 0 512 bulk out (2×) 512 int out (2×) 512
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CY7C68033/CY7C68034 the default NAND firmware image implements an 8-bit data ECCM = 0 bus and up to 8 chip enable pins on the GPIF ports, it is recom- Two 3-byte ECCs, each calculated over a 256-byte block of mended that designs based upon the default firmware image data. This configuration conforms to the SmartMedia Standard use an 8-bit data bus as well. and is used by both the NAND boot logic and default NAND Each GPIF vector defines the state of the control outputs, and firmware image. det
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CY7C68033/CY7C68034 from the default NAND firmware image, which actually utilizes Pin Assignments GPIF Master mode. The signals on the left edge of the ‘Port’ Figure 9 and Figure 10 identify all signals for the 56-pin column are common to all modes of the NX2LP-Flex. The NX2LP-Flex package. 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power-on default configuration. Three modes of operation are available for the NX2LP-Flex: Port mode, GPIF Master mode
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VCC 28 GND 43 *WAKEUP 27 VCC 44 PD0/FD8 26 GND 45 PD1/FD9 25 PB7/FD7 46 PD2/FD10 24 PB6/FD6 47 PD3/FD11 23 PB5/FD5 48 PD4/FD12 22 PB4/FD4 49 PD5/FD13 21 PB3/FD3 50 PD6/FD14 20 PB2/FD2 51 PD7/FD15 19 PB1/FD1 52 GND 18 PB0/FD0 53 GPIO9 17 VCC 54 VCC 16 SDATA 55 GND 15 56 SCL CY7C68033/CY7C68034 Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment RESET# RDY0/*SLRD 1 42 GND RDY1/*SLWR 2 41 PA7/*FLAGD/SLCS# AVCC 3 40 PA6/*PKTEND XTALOUT 4 39 PA5/FIFOADR1 XTALIN 5 38 PA4/FIFOADR0 AGND 6 37 CY7C
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CY7C68033/CY7C68034 [6] Table 8. NX2LP-Flex Pin Descriptions 56 QFN NAND Default Pin Pin Default Pin Firmware Description Name Type State Number Usage 9 DMINUS N/A I/O/Z Z USB D– Signal. Connect to the USB D– signal. 8 DPLUS N/A I/O/Z Z USB D+ Signal. Connect to the USB D+ signal. 42 RESET# N/A Input N/A Active LOW Reset. Resets the entire chip. See section ”Reset and Wakeup” on page 7 for more details. 5 XTALIN N/A Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant
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CY7C68033/CY7C68034 [6] Table 8. NX2LP-Flex Pin Descriptions (continued) 56 QFN NAND Default Pin Pin Default Pin Firmware Description Name Type State Number Usage 13 GPIO8 GPIO8 I/O/Z I GPIO8: is a bidirectional IO port pin. 14 Reserved# N/A Input N/A Reserved. Connect to ground. 2 15 SCL N/A OD Z Clock for the I C interface. Connect to VCC with a 2.2K resistor, 2 even if no I C peripheral is attached. 2 16 SDATA N/A OD Z Data for the I C interface. Connect to VCC with a 2.2K resistor, even
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CY7C68033/CY7C68034 [6] Table 8. NX2LP-Flex Pin Descriptions (continued) 56 QFN NAND Default Pin Pin Default Pin Firmware Description Name Type State Number Usage 39 PA6 or GPIO0 I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] PKTEND (Input) (PA6) bits. PA6 is a bidirectional I/O port pin. PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPIN- POLAR[5]. GPIO1 is a general purpose I/O signal. 40 PA7 or G
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CY7C68033/CY7C68034 [6] Table 8. NX2LP-Flex Pin Descriptions (continued) 56 QFN NAND Default Pin Pin Default Pin Firmware Description Name Type State Number Usage 46 PD1 or CE1# I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] FD[9] (PD1) and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CE1# is a NAND chip enable output signal. 47 PD2 or CE2# or GPIO2 I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] FD[10] (PD2)
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CY7C68033/CY7C68034 Register Summary NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in the TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the NX2LP-Flex should be left at their default power-up values. Table 9. NX2LP-Flex Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF Waveform Memories E400 128 WAVEDATA GPI
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CY7C68033/CY7C68034 Table 9. NX2LP-Flex Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W E62A 1 ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R E62B 1 ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 R E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 R E62D 1 ECC2B0 ECC2 Byte 0 Add
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CY7C68033/CY7C68034 Table 9. NX2LP-Flex Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access [8] E65B 1 NAKIRQ Endpoint Ping-NAK/IBN EP8 EP6 EP4 EP2 EP1 EP0 0 IBN xxxxxx0x bbbbbbrb Interrupt Request E65C 1 USBIE USB Int Enables 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 00000000 RW [8] E65D 1 USBIRQ USB Interrupt Requests 0 EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb E65E 1 EPIE Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0I
