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CY8C24094, CY8C24794
CY8C24894, CY8C24994
®
PSoC Programmable System-on-Chip™
■ Full Speed USB (12 Mbps)
1. Features
❐ Four Uni-Directional Endpoints
■ XRES Pin to Support In-System Serial Programming (ISSP)
❐ One Bi-Directional Control Endpoint
and External Reset Control in CY8C24894
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
■ Powerful Harvard Architecture Processor
❐ No External Crystal Required
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
■ Flexible On-Chip M
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Row Output Configuration Digital Clocks From Core CY8C24094, CY8C24794 CY8C24894, CY8C24994 3.2 The Digital System 3. PSoC Functional Overview The Digital System is composed of four digital PSoC blocks. The PSoC family consists of many Mixed-Signal Array with Each block is an 8-bit resource used alone or combined with On-Chip Controller devices. All PSoC family devices are other blocks to form 8, 16, 24, and 32-bit peripherals, which are designed to replace traditional MCUs, system ICs, and
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 Figure 3-2. Analog System Block Diagram 3.1 The Analog System A ll IO The Analog System is composed of 6 configurable blocks, each (E xcep t P o rt 7) comprised of an opamp circuit allowing the creation of complex P0[7] P0[6] analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. P0[5] P0[4] Some of the more common PSoC analog functions (most P0[3] P0[2] available as user modules)
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 3.1 Additional System Resources 4. Getting Started System Resources, provide additional capability useful to The quickest way to understand PSoC silicon is to read this data complete systems. Additional resources include a multiplier, sheet and then use the PSoC Designer Integrated Development decimator, low voltage detection, and power on reset. Brief state- Environment (IDE). This data sheet is an overview of the PSoC ments describing the merits of e
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 5.1.4 Code Generation Tools 5. Development Tools PSoC Designer supports multiple third party C compilers and ® PSoC Designer is a Microsoft Windows-based, integrated assemblers. The code generation tools work seamlessly within development environment for the Programmable the PSoC Designer interface and have been tested with a full System-on-Chip (PSoC) devices. The PSoC Designer IDE runs range of debugging tools. The choice is yours. on Windows XP or W
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 6.3 Organize and Connect 6. Designing with PSoC Designer You can build signal chains at the chip level by interconnecting The development process for the PSoC device differs from that user modules to each other and the I/O pins, or connect system of a traditional fixed function microprocessor. The configurable level inputs, outputs, and communication interfaces to each analog and digital hardware blocks give the PSoC architecture a other with valuator
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 7.2 Units of Measure 7. Document Conventions A units of measure table is located in the Electrical Specifications 7.1 Acronyms Used section. Table 10-1 on page 20 lists all the abbreviations used to measure the PSoC devices. The following table lists the acronyms that are used in this document. 7.3 Numeric Naming Acronym Description Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ o
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 8. Pin Information This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration. The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O. 8.1 56-Pin Part Pinout [2] Table 8-1. 56-Pin Part Pinout (QFN ) See LEGEND details an
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 8.1 56-Pin Part Pinout (with XRES) [2] Table 8-2. 56-Pin Part Pinout (QFN ) Type Pin Figure 8-2. CY8C24894 56-Pin PSoC Device Name Description No. Digital Analog 1 I/O I, M P2[3] Direct switched capacitor block input. 2 I/O I, M P2[1] Direct switched capacitor block input. 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] A, I, M, P2[3] 1 P2[2], A, I, M 7 I/O M P3[7] 42 A, I, M, P2[1] 2 P2[0], A, I, M 41 8 I/O M P3[5] M, P4[7] 3 40 P4[6], M 9 I
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 8.1 68-Pin Part Pinout The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device. [2] Table 8-3. 68-Pin Part Pinout (QFN ) Type Pin Figure 8-3. CY8C24994 68-Pin PSoC Device Name Description No. Digital Analog 1 I/O M P4[7] 2 I/O M P4[5] 3 I/O MP4[3] 4 I/O MP4[1] 5 NC No connection. 6 NC No connection. 7 Power Vss Ground connection. M, P4[7] P2[0], M, AI 1 51 8 I/O M P3[7] M, P4[5] 2 50 P4[6], M M, P4[3] 9 I/O M P3[5] 3 49 P4[4], M
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 8.1 68-Pin Part Pinout (On-Chip Debug) The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. [2] Table 8-4. 68-Pin Part Pinout (QFN ) Type Pin Figure 8-4. CY8C24094 68-Pin OCD PSoC Device Name Description No. Digital Analog 1 I/O M P4[7] 2 I/O M P4[5] 3 I/O MP4[3] 4 I/O MP4[1] 5 OCDE OCD even data I/O. 6 OCDO OCD odd d
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 8.1 100-Ball VFBGA Part Pinout The 100-ball VFBGA part is for the CY8C24994 PSoC device. Table 8-5. 100-Ball Part Pinout (VFBGA) Pin Pin Name Description Name Description No. No. A1 Power Vss Ground connection. F1 NC No connection. A2 Power Vss Ground connection. F2 I/O M P5[7] A3 NC No connection. F3 I/O M P3[5] A4 NC No connection. F4 I/O M P5[1] A5 NC No connection. F5 Power Vss Ground connection. A6 Power Vdd Supply voltage. F6 Power Vss Groun
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 Figure 8-5. CY8C24094 OCD (Not for Production) 1 2 34 56 78 9 10 Vss Vss NC NC NC Vdd NC NC Vss Vss A Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss B NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC C NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] NC D NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] NC E NC P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] F NC P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] G H NC P5[3] P3[1] P1[5] P1[3]
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 Table 8-6. 100-Ball Part Pinout (VFBGA) (continued) C8 I/O I,M P2[0] Direct switched capacitor block input. H8 I/O M P3[2] C9 I/O MP4[2] H9 I/O M P5[4] C10 NC No connection. H10 I/O P7[3] D1 NC No connection. J1 Power Vss Ground connection. D2 I/O MP3[7] J2 Power Vss Ground connection. D3 I/O MP4[5] J3 USB D+ D4 I/O M P2[5] J4 USB D- D5 I/O I/O, P0[3] Analog column mux input and column output. J5 Power Vdd Supply voltage. M D6 I/O I,M P0[4] Analog colum
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 8.1 100-Pin Part Pinout (On-Chip Debug) The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 8-7. 100-Pin Part Pinout (TQFP) Pin Pin Name Description Name Description No. No. 1 NC No connection. 51 I/O M P1[6] 2 NC No connection. 52 I/O M P5[0] 3 I/O I, M P0[1] Analog column mux input. 53 I/O M P5[2] 4 I/O M P2[7] 54 I/O M P5[4] 5 I/O
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 Table 8-7. 100-Pin Part Pinout (TQFP) (continued) LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger. Figure 8-7. CY8C24094 OCD (Not for Production) NC NC 1 75 NC 74 P 0 [0 ], M , A I 2 AI, M , P 0 [1 ] 3 NC 73 M,P2 [7] 4 72 P 2 [6 ], M ,Ex te rn al VREF M,P2 [5] 71 5 NC AI, M , P 2 [3 ] 70 6 P 2 [4 ], M ,Ex te rn al AG ND AI, M , P 2 [1 ] 69 7 P 2 [2 ], M , A I M,P4 [7] P 2 [0 ], M , A I 8 68 M,P4
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 9. Register Reference This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual. 9.1 Register Conventions 9.2 Register Mapping Tables The register conventions specific to this section are listed in the The PSoC device has a total register address space of 512 following table. bytes. The register space is referred to as I/O space a
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 9.3 Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW PMA0_DR 40 RW ASC10CR0 80 RW C0 PRT0IE 01 RW PMA1_DR 41 RW ASC10CR1 81 RW C1 PRT0GS 02 RW PMA2_DR 42 RW ASC10CR2 82 RW C2 PRT0DM2 03 RW PMA3_DR 43 RW ASC10CR3 83 RW C3 PRT1DR 04 RW PMA4_DR 44 RW ASD11CR0 84 RW C4 PRT1IE 05 RW PMA5_DR 45 RW ASD11CR1 85 RW C5 PRT1GS 06 RW PMA6_DR 46 RW ASD11CR2 86 RW C
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CY8C24094, CY8C24794 CY8C24894, CY8C24994 9.4 Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access PRT0DM0 00 RW PMA0_WA 40 RW ASC10CR0 80 RW USBI/O_CR2 C0 RW PRT0DM1 01 RW PMA1_WA 41 RW ASC10CR1 81 RW USB_CR1 C1 # PRT0IC0 02 RW PMA2_WA 42 RW ASC10CR2 82 RW PRT0IC1 03 RW PMA3_WA 43 RW ASC10CR3 83 RW PRT1DM0 04 RW PMA4_WA 44 RW ASD11CR0 84 RW EP1_CR0 C4 # PRT1DM1 05 RW PMA5_WA 45 RW ASD11CR1 85 RW EP2
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Valid Opera ting Region CY8C24094, CY8C24794 CY8C24894, CY8C24994 10. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. o o o Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C, except where noted. Specifications for devices running at greater than A J o o o 12 M
