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CY7C1380C
CY7C1382C
18-Mb (512K x 36/1M x 18) Pipelined SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
• Available speed grades are 250, 225, 200,166 and
peripheral circuitry and a two-bit counter for internal burst
133MHz
operation. All synchronous inputs are gated by registers
• Registered inputs and outputs for pipelined operation
controlled by a po
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CY7C1380C CY7C1382C 1 Logic Block Diagram – CY7C1380C (512K x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV Q1 CLK BURST COUNTER AND CLR Q0 LOGIC ADSC ADSP DQD ,DQPD DQD ,DQPD BYTE BYTE BWD WRITE REGISTER WRITE DRIVER DQC ,DQPC DQC ,DQPC BYTE BWC BYTE OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQPA DQB ,DQPB E DQB ,DQPB DQPB BYTE BYTE BWB DQPC WRITE DRIVER WRITE REGISTER DQPD DQA ,DQPA DQA ,DQPA BYTE BYTE BWA WRITE DRIVER WRITE REG
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CY7C1380C CY7C1382C Pin Configurations 100-pin TQFP Pinout DQP C 1 80 DQPB NC A 1 80 DQC 2 79 DQB NC NC 2 79 DQc 3 78 DQB NC NC 3 78 V DDQ V 4 77 V DDQ DDQ 4 77 V DDQ V SSQ V 5 76 V SSQ SSQ 5 76 V SSQ DQC DQB 6 75 NC 6 75 NC DQC DQB 7 74 NC 7 74 DQPA DQC DQB 8 73 DQB 8 73 DQA DQC 9 72 DQB DQB DQA 9 72 V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQC 12 69 DQB DQB DQA 12 69 DQC DQB 13 68 DQB DQA 13 68 NC V 14 67 NC SS 14 67 V SS V DD NC 15 66 V DD 15 CY7C1382C 66 NC CY
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CY7C1380C CY7C1382C Pin Configurations (continued) 119-ball BGA (1 Chip Enable with JTAG) CY7C1380C (512K x 36) 1 23 4 5 6 7 A V AA A A V ADSP DDQ DDQ B NC AA ADSC A A NC C NC A A V A A NC DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V CE V DQ DQ C C SS 1 SS B B F V DQ V V DQ V DDQ C SS OE SS B DDQ G DQ DQ BW BW DQ DQ ADV C C C B B B H DQ DQ V V DQ DQ GW C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D A A D A M V DQ V V DQ V BWE
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CY7C1380C CY7C1382C Pin Configurations (continued) 165-ball fBGA CY7C1380C (512K x 36) 1 2 3 4 567 89 10 11 NC / 288M A NC A A CE BW BW CE ADSC BWE ADV 1 C B 3 NC A CE2 BW BW CLK A NC / 144M B GW OE ADSP D A NC V V V V V NC DQP C DQP V V C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B
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CY7C1380C CY7C1382C CY7C1380C–Pin Definitions Name TQFP BGA fBGA I/O Description A , A , A 37,36,32, P4,N4, R6,P6,A2, Input- Address Inputs used to select one of the 0 1 33,34,35, A2,B2, A10,B2, Synchronous 256K address locations. Sampled at the rising 42,43,44,45, C2,R2, B10,N6,P3,P4, edge of the CLK if or is active ADSP ADSC [2] 46,47,48, A3,B3,C3, P8,P9,P10, LOW, and CE , CE , and CE are sampled 1 2 3 49,50,81, T3,T4,A5,B5, P11,R3,R4,R8, active. A1: A0 are fed to the two-bit counter. .
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CY7C1380C CY7C1382C CY7C1380C–Pin Definitions (continued) Name TQFP BGA fBGA I/O Description 84 A4 B9 Input- Address Strobe from Processor, sampled ADSP Synchronous on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH. 1 B4 A8 Input- Address Strobe from Controll
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CY7C1380C CY7C1382C CY7C1380C–Pin Definitions (continued) Name TQFP BGA fBGA I/O Description V 5,10,21,26,55, - - I/O Ground Ground for the I/O circuitry. SSQ 60,71, 76 V 4,11,20,27,54, A1,F1,J1,M1, C3,C9,D3,D9, I/O Power Power supply for the I/O circuitry. DDQ 61,70, U1, E3,E9,F3,F9,G Supply 77 A7,F7,J7,M7, 3, U7 G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 MODE 31 R3 R1 Input- Selects Burst Order. When tied to GND Static selects linear burst sequence. When tied to V DD or left floating selects inte
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CY7C1380C CY7C1382C CY7C1382C:Pin Definitions Name TQFP BGA fBGA I/O Description A , A , A 37,36,32, P4,N4, R6,P6,A2, Input- Address Inputs used to select one of the 512K 0 1 33,34,35, A2,B2, A10,A11, Synchronous address locations. Sampled at the rising edge of 42,43,44, C2,R2, B2,B10,P3,P4, the CLK if or is active LOW, and CE , ADSP ADSC 1 45,46,47, T2,A3, N6,P8,P9, CE , and CE are sampled active. A1: A0 are fed 2 3 48,49,50, B3,C3, P10,P11, to the two-bit counter. . 80,81,82, T3,A5, R3,
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CY7C1380C CY7C1382C CY7C1382C:Pin Definitions (continued) Name TQFP BGA fBGA I/O Description 84 A4 B9 Input- Address Strobe from Processor, sampled on ADSP Synchronous the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH. 1 P4 A8 Input- Address Strobe from Controlle
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CY7C1380C CY7C1382C CY7C1382C:Pin Definitions (continued) Name TQFP BGA fBGA I/O Description V 4,11,20,27,54, A1,A7,F1,F7, C3,C9,D3,D9, I/O Power Sup- Power supply for the I/O circuitry. DDQ 61,70, J1,J7,M1,M7, E3,E9, ply 77 U1,U7 F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 MODE 31 R3 R1 Input- Selects Burst Order. When tied to GND selects Static linear burst sequence. When tied to V or left DD floating selects interleaved burst sequence. This is a strap pin and should remain static during
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CY7C1380C CY7C1382C Functional Overview All synchronous inputs pass through input registers controlled presented to A is loaded into the address register and the by the rising edge of the clock. All data outputs pass through address advancement logic while being delivered to the output registers controlled by the rising edge of the clock. memory array. The Write signals (GW, BWE, and BW ) and X Maximum access delay from the clock rise (t ) is 3.0ns ADV inputs are ignored during this first cycle.
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CY7C1380C CY7C1382C Asserting ADV LOW at clock rise will automatically increment Sleep Mode the burst counter to the next address in the burst sequence. The ZZ input pin is an asynchronous input. Asserting ZZ Both Read and Write burst operations are supported. places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” Interleaved Burst Address Table mode. While in this mode, data integrity is guaranteed. (MODE = Floating or V ) DD
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CY7C1380C CY7C1382C [ 3, 4, 5, 6, 7, 8] Truth Table Operation Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 2 3 1 READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend
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CY7C1380C CY7C1382C Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1380C incorporates a serial boundary scan test and is sampled on the rising edge of TCK. It is allowable to access port (TAP). This port operates in accordance with IEEE leave this ball unconnected if the TAP is not used. The ball is Standard 1149.1-1990 but does not have the set of functions pulled up internally, resulting in a logic HIGH level.
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CY7C1380C CY7C1382C TDI and TDO balls as shown in the Tap Controller Block To execute the instruction once it is shifted in, the TAP Diagram. Upon power-up, the instruction register is loaded controller needs to be moved into the Update-IR state. with the IDCODE instruction. It is also loaded with the IDCODE EXTEST instruction if the controller is placed in a reset state as described in the previous section. EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instructio
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CY7C1380C CY7C1382C Note that since the PRELOAD part of the command is not register is placed between the TDI and TDO balls. The implemented, putting the TAP to the Update-DR state while advantage of the BYPASS instruction is that it shortens the performing a SAMPLE/PRELOAD instruction will have the boundary scan path when multiple devices are connected same effect as the Pause-DR command. together on a board. Reserved BYPASS These instructions are not implemented but are reserved for When the B
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CY7C1380C CY7C1382C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ........ ........................................VSS to 3.3V Input pulse levels...............................................VSS to 2.5V Input rise and fall times...................... ..............................1ns Input rise and fall time ......................................................1ns Input timing reference levels...........................................1.5V Input timing reference l
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CY7C1380C CY7C1382C Identification Register Definitions CY7C1380C CY7C1382C DESCRIPTION INSTRUCTION FIELD (512KX36) (1MX18) 010 0100 Revision Number (31:29) Describes the version number. Device Depth (28:24) 01010 1010 Reserved for Internal Use Device Width (23:18) 000000 000000 Defines memory type and architecture Cypress Device ID (17:12) 100101 010101 Defines width and density Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. 11 ID Register Pres
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CY7C1380C CY7C1382C 119-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1 37 B2 K4 2 38 P4 H4 3M4 39 N4 4F4 40 R6 5B4 41 T5 6A4 42 T3 7G4 43 R2 8C6 44 R3 9A6 45 P2 10 D6 46 P1 11 D7 47 N2 12 E6 48 L2 13 G6 49 K1 14 H7 50 N1 15 E7 51 M2 16 F6 52 L1 17 G7 53 K2 18 H6 54 Not Bonded (Preset to 1) 19 T7 55 H1 20 K7 56 G2 21 L6 57 E2 22 N6 58 D1 23 P7 59 H2 24 K6 60 G1 25 L7 61 F2 26 M6 62 E1 27 N7 63 D2 28 P6 64 A5 29 B5 65 A3 30 B3 66 E4 31 C5 67 Internal 32 C3 68 L3 33
