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CY7C1297H
1-Mbit (64K x 18) Flow-Through Sync SRAM
[1]
Features Functional Description
The CY7C1297H is a 64K x 18 synchronous cache RAM
• 64K x 18 common I/O
designed to interface with high-speed microprocessors with
• 3.3V core power supply (V )
DD
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
• 2.5V/3.3V I/O power supply (V )
DDQ
first address in a burst and increments the address automati-
• Fast clock-to-output ti
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CY7C1297H Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum Standby Current 40 40 mA Pin Configuration 100-Pin TQFP NC 1 80 A NC 2 79 NC NC 3 78 NC V 4 DDQ 77 V DDQ V 5 SS 76 V SS NC 6 75 NC NC 7 74 DQP A DQ 8 B 73 DQ A DQ 9 B 72 DQ A V 10 SS 71 V SS V 11 DDQ 70 V DDQ DQ 12 DQ B 69 A DQ 13 DQ B 68 A NC 14 67 V SS V 15 CY7C1297H DD 66 NC NC 16 65 V BYTE A DD BYTE B V 17 ZZ SS 64 DQ 18 B 63 DQ A DQ 19 B 62 DQ A V 20 DDQ 61 V DDQ V 2
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CY7C1297H Pin Descriptions Name I/O Description A0, A1, A Input- Address Inputs used to select one of the 64K address locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A 1 2 3 [1:0] feed the 2-bit counter. BW , BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. A B Synchronous Sampled on the rising edge of CLK. GW Input- Global Write Enable Input, active LOW.
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CY7C1297H active, (2) ADSC is asserted LOW, (3) ADSP is deasserted Functional Overview HIGH, and (4) the Write input signals (GW, BWE, and BW ) [A:B] All synchronous inputs pass through input registers controlled indicate a write access. ADSC is ignored if ADSP is active by the rising edge of the clock. Maximum access delay from LOW. the clock rise (t ) is 6.5 ns (133-MHz device). CDV The addresses presented are loaded into the address register The CY7C1297H supports secondary cache in systems
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CY7C1297H ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep mode standby current ZZ > V – 0.2V 40 mA DDZZ DD t Device operation to ZZ ZZ > V – 0.2V 2t ns ZZS DD CYC t ZZ recovery time ZZ < 0.2V 2t ns ZZREC CYC t ZZ Active to sleep current This parameter is sampled 2t ns ZZI CYC t ZZ Inactive to exit sleep current This parameter is sampled 0 ns RZZI [2, 3, 4, 5, 6] Truth Table Cycle Description Address Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1
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CY7C1297H [2, 3] Truth Table for Read/Write Function GW BWE BW BW B A Read H H X X Read H L H H Write Byte (A, DQP)HLHL A Write Byte (B, DQP)HLLH B Write All Bytes H L L L Write All Bytes L X X X Document #: 38-05669 Rev. *B Page 6 of 15 [+] Feedback
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CY7C1297H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch-up Current.....................................................
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CY7C1297H [9] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V. DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [9] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods and 30.32 °C/W JA (Junction to Ambient) procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resistanc
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CY7C1297H [10, 11] Switching Characteristics Over the Operating Range 133 MHz 100 MHz Parameter Description Min. Max. Min. Max. Unit [12] t V (Typical) to the First Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10.0 ns CYC t Clock HIGH 2.5 4.0 ns CH t Clock LOW 2.5 4.0 ns CL Output Times t Data Output Valid after CLK Rise 6.5 8.0 ns CDV t Data Output Hold after CLK Rise 2.0 2.0 ns DOH [13, 14, 15] t Clock to Low-Z 00 ns CLZ [13, 14, 15] t Clock to High-Z 3.5 3.5 ns CHZ OE LOW to Output Vali
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CY7C1297H Timing Diagrams [16] Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADH ADS ADSC t t AH AS ADDRESS A1 A2 t t WES WEH GW, BWE,BW [A:B] Deselect Cycle t t CES CEH CE t t ADVH ADVS ADV ADV suspends burst. OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Data Out (Q) Q(A1) High-Z t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 16. On this diagram, when CE is LOW, CE is
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CY7C1297H Timing Diagrams (continued) [16, 17] Write Cycle Timing t CYC CLK t t CL CH t t ADH ADS ADSP ADSC extends burst. t t ADS ADH t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst. t t WEH WES BWE, BW[A:B] t t WES WEH GW t t CEH CES CE t t ADVS ADVH ADV ADV suspends burst. OE t t DH DS Data in (D) D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z t OEHZ Data Out (Q) BURST READ Single
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CY7C1297H Timing Diagrams (continued) [16, 18, 19] Read/Write Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC t t AS AH A1 A2 A3 A4 A5 A6 ADDRESS t t WEH WES BWE, BW[A:B] t t CES CEH CE ADV OE t t DS DH t OELZ High-Z D(A3) D(A5) D(A6) Data In (D) t OEHZ t CDV Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or AD
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CY7C1297H Timing Diagrams (continued) [20, 21] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05669 Rev. *B Page 13 of 15 [+] Feedback
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CY7C1297H Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 100 CY7C1297H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1297H-100AXI Industrial 133 CY7C1297H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1
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CY7C1297H Document History Document Title: CY7C1297H 1-Mbit (64K x 18) Flow-Through Sync SRAM Document Number: 38-05669 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 345879 See ECN PCI New Data Sheet *A 430677 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added 2.5VI/O option Changed Three-State to Tri-State Included Maximum Ratings for V relative to GND DDQ Modified “Input Load” to “Input
