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PRELIMINARY
CY14B108K, CY14B108M
8 Mbit (1024K x 8/512K x 16) nvSRAM with
Real Time Clock
■ Watchdog timer
Features
■ Clock alarm with programmable interrupts
■ 20 ns, 25 ns, and 45 ns access times
■ Capacitor or battery backup for RTC
■ Internally organized as 1024K x 8 (CY14B108K) or 512K x 16
(CY14B108M)
■ Commercial and industrial temperatures
■ Hands off automatic STORE on power down with only a small
■ 44 and 54-pin TSOP II package
capacitor
■ Pb-free and RoHS compliance
®
■ STORE to Qua
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PRELIMINARY CY14B108K, CY14B108M Pinouts Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II INT 54 HSB 1 INT 1 44 HSB [4] [4] NC 53 A 2 18 NC 2 NC 43 A A 0 52 3 17 A 3 42 A 0 19 A 51 A 1 4 16 A 4 A 1 41 18 A 50 A 2 5 15 A 5 A 49 2 40 A OE 17 3 6 48 A A BHE 6 39 A 4 7 3 16 47 CE 8 BLE A 7 38 4 A 15 DQ 46 DQ 0 9 15 CE 8 37 OE 54 - TSOP II DQ 10 45 DQ 1 14 DQ 9 44 - TSOP II DQ 0 36 7 DQ 11 44 DQ 2 (x16) 13 (x8) DQ 10 35 DQ 1 DQ 43 DQ 6 12 3 12 V 11 V 42 CC 34 V CC V 13 SS Top View SS Top View 12 V
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PRELIMINARY CY14B108K, CY14B108M Table 1. Pin Definitions (continued) Pin Name I/O Type Description Output Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power INT monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). V Ground Ground for the Device. Must be connected to ground of the system. SS V Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%. CC Input/Output Hardware STORE Busy (HSB). When LOW this outp
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PRELIMINARY CY14B108K, CY14B108M power-on-recall, the MPU must be active or the WE held inactive To initiate the Software STORE cycle, the following read until the MPU comes out of reset. sequence must be performed: 1. Read address 0x4E38 Valid READ To reduce unnecessary nonvolatile STOREs, AutoStore, and Hardware STORE operations are ignored unless at least one 2. Read address 0xB1C7 Valid READ write operation has taken place since the most recent STORE or 3. Read address 0x83E0 Valid READ RECA
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PRELIMINARY CY14B108K, CY14B108M Table 2. Mode Selection [3] [5] Mode I/O Power A - A CE WE OE, BHE, BLE 15 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active [6] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable [6] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Dat
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PRELIMINARY CY14B108K, CY14B108M Data Protection Best Practices The CY14B108K/CY14B108M protects data from corruption nvSRAM products have been used effectively for over 15 years. during low voltage conditions by inhibiting all externally initiated While ease-of-use is one of the product’s main system values, STORE and write operations. The low voltage condition is experience gained working with hundreds of applications has detected when V is less than V . If the resulted in the following sugges
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PRELIMINARY CY14B108K, CY14B108M nonvolatile memory. Therefore, while working in AutoStore Real Time Clock Operation disabled mode, the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly. nvTime Operation The CY14B108K/CY14B108M offers internal registers that Backup Power contain clock, alarm, watchdog, interrupt, and control functions. The RTC in the CY14B108K is intended for permanently RTC registers use the last 16 address locations of the S
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PRELIMINARY CY14B108K, CY14B108M calibration registers and the OSCEN bit are not affected by the alarm internal flag (AF) is set and an interrupt is generated on ‘oscillator failed’ condition. INT pin if Alarm Interrupt Enable (AIE) bit is set. The value of OSCF must be reset to ‘0’ when the time registers There are four alarm match fields - date, hours, minutes, and are written for the first time. This initializes the state of this bit seconds. Each of these fields has a match bit that is used
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PRELIMINARY CY14B108K, CY14B108M Figure 3. Watchdog Timer Block Diagram output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended Clock Oscillator to reset a host microcontroller. In the level mode, the pin goes to 1 Hz Divider its active polarity until the Flags register is read by the user. This 32,768 KHz 32 Hz mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section. Zero
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PRELIMINARY CY14B108K, CY14B108M Figure 4. RTC Recommended Component Configuration Recommended Values Y = 32.768 KHz (6 pF) 1 C = 21 pF 1 C = 21 pF 2 Note: The recommended values for C1 and C2 include board trace capacitance. C1 X out Y1 C2 X in Figure 5. Interrupt Block Diagram WDF Watchdog WDF - Watchdog Timer Flag Timer WIE WIE - Watchdog Interrupt Enable V P/L CC PF PF - Power Fail Flag Power PFE - Power Fail Enable Pin Monitor INT AF - Alarm Flag PFE Driver AIE - Alarm Interrupt Ena
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PRELIMINARY CY14B108K, CY14B108M [7] Table 4. RTC Register Map [8] Register BCD Format Data Function/Range CY14B108K CY14B108M D7 D6 D5 D4 D3 D2 D1 D0 0xFFFFF 0x7FFFF 10s Years Years Years: 00–99 0xFFFFE 0x7FFFE 0 0 0 10s Months Months: 01–12 Months 0xFFFFD 0x7FFFD 0 0 10s Day of Month Day Of Month Day of Month: 01–31 0xFFFFC 0x7FFFC 0 0 0 0 0 Day of week Day of week: 01–07 0xFFFFB 0x7FFFB 0 0 10s Hours Hours Hours: 00–23 0xFFFFA 0x7FFFA 0 10s Minutes Minutes Minutes: 00–59 0xFFFF9 0x7FFF9 0 10
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PRELIMINARY CY14B108K, CY14B108M Table 5. Register Map Detail Register Description CY14B108K CY14B108M Time Keeping - Years 0xFFFFF 0x7FFFF D7 D6 D5 D4 D3 D2 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Time Keeping - Months 0xFFFFE 0x7FFFE D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10s Month Month
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PRELIMINARY CY14B108K, CY14B108M Table 5. Register Map Detail (continued) Register Description CY14B108K CY14B108M Calibration/Control 0xFFFF8 0x7FFF8 D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibration Calibration Sign OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0
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PRELIMINARY CY14B108K, CY14B108M Table 5. Register Map Detail (continued) Register Description CY14B108K CY14B108M Alarm - Hours 0xFFFF4 0x7FFF4 D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes 0xFFFF3 0x7FFF3 D7 D6 D5 D4 D3 D2
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PRELIMINARY CY14B108K, CY14B108M Transient Voltage (<20 ns) on Maximum Ratings Any Pin to Ground Potential .................. –2.0V to V + 2.0V CC Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device. These user guidelines are not tested. Capability (T = 25°C) ................................................... 1.0W A Storage Temperature ................................. –65 °C to +150 °C Surface Mount Pb Soldering Temperature (3 Seconds)................
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PRELIMINARY CY14B108K, CY14B108M Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [13] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 14 pF IN A V = 0 to 3.0V CC C Output Capacitance 14 pF OUT Thermal Resistance [13] In the following table, the thermal resistance parameters are listed. Parameter D
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PRELIMINARY CY14B108K, CY14B108M Table 6. RTC Characteristics Parameters Description Test Conditions Min Typ Max Units [14] o I RTC Backup Current Room Temperature (25 C) 300 nA BAK o Hot Temperature (85 C) 450 nA V RTC Battery Pin Voltage 1.8 3.0 3.3 V RTCbat V RTC Capacitor Pin Voltage 1.5 3.0 3.6 V RTCcap tOCS RTC Oscillator Time to Start 1 2 sec Note 14. From either V or V RTCcap RTCbat. Document #: 001-47378 Rev. ** Page 17 of 29 [+] Feedback
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PRELIMINARY CY14B108K, CY14B108M AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [15] t t Read Cycle Time 20 25 45 ns RC RC [16] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE [16] t t Output Hold After Address Change 3 3 3 ns OHA OH [13, 17] t t Chip Enable to Output Active 3 3 3 ns LZCE LZ [13, 17] t
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PRELIMINARY CY14B108K, CY14B108M Switching Waveforms [3, 15, 19] Figure 8. SRAM Read Cycle 2: CE Controlled Address Address Valid t t RC HZCE t ACE CE t AA t t LZCE HZOE t DOE OE t t HZBE LZOE t DBE BHE, BLE t LZBE High Impedance Data Output Output Data Valid t PU t PD Active I Standby CC [3, 18, 19, 20] Figure 9. SRAM Write Cycle 1: WE Controlled t WC Address Address Valid t t SCE HA CE t BW BHE, BLE t AW t PWE WE t SA t t HD SD Data Input Input Data Valid t t LZWE HZWE High Impedance Data O
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PRELIMINARY CY14B108K, CY14B108M Switching Waveforms [3, 18, 19, 20] Figure 10. SRAM Write Cycle 2: CE Controlled t WC Address Valid Address t t t SA SCE HA CE t BW BHE, BLE t PWE WE t t HD SD Data Input Input Data Valid High Impedance Data Output [5, 18, 19, 20, 21] Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled (Not applicable for RTC register writes) t WC Address Address Valid t SCE CE t t t SA HA BW BHE, BLE t AW t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Ou
