Instrukcja obsługi Cypress CY14E102L

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ADVANCE
CY14E102L, CY14E102N
2-Mbit (256K x 8/128K x 16) nvSRAM
Features Functional Description
■ 15 ns, 20 ns, 25 ns, and 45 ns access times The Cypress CY14E102L/CY14E102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 256K x 8 (CY14E102L) or 128K x 16
organized as 256K words of 8 bits each or 128K words of 16 bits
(CY14E102N)
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most re

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CY14E102L, CY14E102N ADVANCE Pinouts Figure 1. Pin Diagram - 48 FBGA (Top View) (x16) (x8) (Not to Scale) (Not to Scale) 1 2 4 5 3 6 1 2 3 4 5 6 A A A OE NC A A A BLE 0 2 A NC OE NC 1 0 1 2 A DQ8 A A NC BHE CE DQ0 B NC A A 3 4 CE NC B 3 4 C DQ9 A A DQ1 DQ2 A A C DQ10 DQ0 NC NC DQ4 5 6 5 6 [2] V A V A V DQ3 V A SS DQ11 7 CC D SS DQ1 7 DQ5 CC D NC 17 A V V E V A V E CC DQ12 V DQ4 SS CC DQ2 V DQ6 SS CAP 16 CAP 16 F A A F A A DQ14 DQ13 DQ6 DQ3 NC NC DQ7 14 15 DQ5 14 15 [4] A A A A G G DQ15 HSB WE

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CY14E102L, CY14E102N ADVANCE Pinouts (continued) Figure 3. Pin Diagram - 54 TSOP II (Top View) NC 54 HSB 1 [4] [3] NC 53 NC 2 [2] A 0 52 NC 3 A 51 A 1 4 16 A 50 A 2 5 15 49 A OE 3 6 48 A BHE 4 7 47 CE 8 BLE DQ0 46 DQ15 9 DQ1 45 DQ14 10 DQ2 11 44 DQ13 (x16) 43 DQ3 12 DQ12 (Not to Scale) V 42 CC 13 V SS V 41 V SS 14 CC DQ4 40 DQ11 15 39 DQ5 DQ10 16 38 DQ6 DQ9 17 37 DQ7 DQ8 18 36 WE V 19 CAP 35 A A 5 20 14 34 A A 6 21 13 33 A A 22 7 12 32 A A 23 11 8 31 A A 24 9 10 30 NC 25 NC 26 29 NC NC 27 NC 2

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CY14E102L, CY14E102N ADVANCE To reduce unnecessary nonvolatile stores, AutoStore and Device Operation Hardware Store operations are ignored unless at least one The CY14E102L/CY14E102N nvSRAM is made up of two WRITE operation has taken place since the most recent STORE functional components paired in the same physical cell. They are or RECALL cycle. Software initiated STORE cycles are an SRAM memory cell and a nonvolatile QuantumTrap cell. The performed regardless of whether a WRITE operation has

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CY14E102L, CY14E102N ADVANCE The software sequence may be clocked with CE controlled Hardware RECALL (Power Up) READs or OE controlled READs. After the sixth address in the sequence is entered, the STORE cycle commences and the chip During power up or after any low power condition is disabled. It is important to use READ cycles and not WRITE (V

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CY14E102L, CY14E102N ADVANCE Table 1. Mode Selection (continued) A15 - A0 Mode IO Power CE WE OE [5,6,7] L H L 0x4E38 Read SRAM Output Data Active I CC2 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Store Output High Z [5,6,7] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Outpu

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CY14E102L, CY14E102N ADVANCE Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260 °C [8] Storage Temperature ................................. –65 °C to +150 °C Output Short Circuit Current ...................................

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CY14E102L, CY14E102N ADVANCE Capacitance [11] The following table lists the capacitance parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [11] The following table lists the thermal resistance parameters. Parameter Description Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit Θ Thermal Resistance Test conditions follow standard test methods and 28.82 31.11 30.73 °C/W JA

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CY14E102L, CY14E102N ADVANCE AC Switching Characteristics The following table lists the AC switching characteristics. Parameters 15 ns 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 15 20 25 45 ns ACE ACS [12] t t Read Cycle Time 15 20 25 45 ns RC RC [13] t t Address Access Time 15 20 25 45 ns AA AA t t Output Enable to Data Valid 10 10 12 20 ns DOE OE t t Output Hold After Address 333 3 ns OHA OH

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CY14E102L, CY14E102N ADVANCE AutoStore and Power Up RECALL CY14E102L/CY14E102N Parameters Description Unit Min Max [16] t Power Up RECALL Duration 20 ms HRECALL [17] t STORE Cycle Duration 15 ms STORE V Low Voltage Trigger Level 4.4 V SWITCH t VCC Rise Time 150 μs VCCRISE Software Controlled STORE and RECALL Cycle [18, 19] The following table lists the software controlled STORE and RECALL cycle parameters. 15ns 20 ns 25ns 45ns Parameters Description Unit Min Max Min Max Min Max Min Max t STORE

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CY14E102L, CY14E102N ADVANCE Switching Waveforms [12, 13, 23] Figure 5. SRAM Read Cycle #1: Address Controlled t RC ADDRESS t AA t OHA DQ (DATA OUT) DATA VALID [12, 23, 25] Figure 6. SRAM Read Cycle #2: CE and OE Controlled t RC ADDRESS t ACE t PD CE t LZCE t HZCE OE t HZOE t DOE t LZOE BHE , BLE t HZCE t HZBE t DBE t LZBE DQ (DATA OUT) DATA VALID ACTIVE t PU STANDBY ICC Notes 23. HSB must remain HIGH during READ and WRITE cycles. 24. CE or WE must be >V during address transitions. IH

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CY14E102L, CY14E102N ADVANCE Switching Waveforms (continued) [13, 21, 22, 23] Figure 7. SRAM Write Cycle #1: WE Controlled tWC ADDRESS t HA tSCE CE t AW t SA t PWE WE tBW BHE , BLE t t SD HD DATA IN DATA VALID t HZWE t LZWE HIGH IMPEDANCE DATA OUT PREVIOUS DATA [13, 21, 22, 23] Figure 8. SRAM Write Cycle #2: CE Controlled t WC ADDRESS t SA t SCE CE t HA t AW t WE PWE t BW BHE , BLE t t SD HD DATA IN DATA VALID HIGH IMPEDANCE DATA OUT Document Number: 001-45755 Rev. *A Page 12 of 21 [+] Fee

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CY14E102L, CY14E102N ADVANCE Switching Waveforms (continued) [26] Figure 9. AutoStore or Power Up RECALL STORE occurs only No STORE occurs if a SRAM write without atleast one has happened SRAM write V CC V SWITCH t VCCRISE AutoStore t t STORE STORE POWER-UP RECALL t t HRECALL HRECALL Read & Write Inhibited [19] Figure 10. CE Controlled Software STORE/RECALL Cycle Note 26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V . SWITCH Document Number: 001-45755 Rev

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CY14E102L, CY14E102N ADVANCE Switching Waveforms (continued) [19] Figure 11. OE Controlled Software STORE/RECALL Cycle t t RC RC ADDRESS # 1 ADDRESS # 6 ADDRESS CE t t AS CW OE t GHAX t / t STORE RECALL HIGH IMPEDANCE DQ (DATA) DATA VALID DATA VALID [22] Figure 12. Hardware STORE Cycle [20, 21] Figure 13. Soft Sequence Processing t t SS SS Document Number: 001-45755 Rev. *A Page 14 of 21 [+] Feedback

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CY14E102L, CY14E102N ADVANCE Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 15 CY14B102L-ZS15XCT 51-85087 44-pin TSOP II Commercial CY14E102L-ZS15XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS15XI 51-85087 44-pin TSOP II CY14E102L-BA15XCT 51-85128 48-ball FBGA Commercial CY14E102L-BA15XIT 51-85128 48-ball FBGA Industrial CY14E102L-BA15XI 51-85128 48-ball FBGA CY14E102L-ZSP15XCT 51-85160 54-pin TSOP II Commercial CY14E102L-ZSP15XIT 51-85160 54-pin

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CY14E102L, CY14E102N ADVANCE Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 25 CY14E102L-ZS25XCT 51-85087 44-pin TSOP II Commercial CY14E102L-ZS25XIT 51-85087 44-pin TSOP II Industrial CY14E102L-ZS25XI 51-85087 44-pin TSOP II CY14E102N-BA25XCT 51-85128 48-ball FBGA Commercial CY14E102L-BA25XIT 51-85128 48-ball FBGA Industrial CY14E102L-BA25XI 51-85128 48-ball FBGA CY14E102L-ZSP25XCT 51-85160 54-pin TSOP II Commercial CY14E102L-ZSP25XIT 51-8

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CY14E102L, CY14E102N ADVANCE Part Numbering Nomenclature CY 14 E 102 L - ZS P 15 X C T Option: T - Tape & Reel Temperature: Blank - Std. C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Speed: Pb-Free 15 - 15 ns 20 - 20 ns 25 - 25 ns Package: 45 - 45 ns P - 54 Pin Blank - 44 Pin BA - 48 FBGA Data Bus: ZS - TSOP II L - x8 N - x16 Density: 102 - 2 Mb Voltage: E - 5.0V NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document Number: 001-45755 Rev. *A Page 17 of 21 [+] Fee

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CY14E102L, CY14E102N ADVANCE Package Diagrams Figure 14. 44-Pin TSOP II DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document Number: 001-45755 Rev. *A Page 18 of 21 [+] Feedback 1.194 (0.047) 0.991 (0.039) 0.150 (0.

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CY14E102L, CY14E102N ADVANCE Package Diagrams (continued) Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85128-*D Document Number: 001-45755 Rev. *A Page 19 of 21 [+] Feedback 0.25 C 10.00±0.10 0.36 0.53±0.05 0.21±0.05 1.20 MAX 0.15 C 10.00±0.10 5.25 0.75 2.625

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CY14E102L, CY14E102N ADVANCE Package Diagrams (continued) Figure 16. 54-Pin TSOP II 51-85160-** Document Number: 001-45755 Rev. *A Page 20 of 21 [+] Feedback