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Preliminary Information
AMD Athlon™ Processor Model 6
Revision Guide
Publication # 24332 Rev: E
Issue Date: December 2002
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Preliminary Information © 2001, 2002 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide Revision History Date Rev Description December 2002 E Added errata #22–24. July 2002 D Added errata #20 and #21. ■ Added silicon revision A5 information ■ Added erratum #18 and #19 October 2001 C ■ Added Table 2: Cross-reference of Erratum to Processor Segments to include all processor segments ■ Updated reference documents listed in section 3.1 May 2001 B Initial public release. 3
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 AMD Athlon™ Processor Model 6 Revision Guide The purpose of the AMD Athlon™ Processor Model 6 Revision Guide is to communicate updated product information on the AMD Athlon processor model 6 to designers of computer systems and software developers. This revision guide applies to the AMD Athlon processor model 6, mobile AMD Athlon processor model 6, and AMD Athlon MP processor model 6. This guide consis
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 1 Product Errata This section documents AMD Athlon™ Processor Model 6 product errata. The errata are divided into categories to assist referencing particular errata. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 1 cross-references the revisions of the processor to each erratum. An “X” ind
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 Table 2. Cross-Reference of Erratum to Processor Segments Errata 1 2 3 Workstation/Server Desktop Mobile Number XX X 16 X 17 X 18 XX X 19 XX X 20 XX X 21 XX X 22 XX X 23 XX X 24 Notes: 1. The workstation/server segment currently includes the AMD Athlon™ MP processor. 2. The desktop segment currently includes the AMD Athlon XP processor. 3. The mobile segment currently includes the AMD Athlon 4 process
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addresses Products Affected. A0, A2 Normal Specified Operation. After executing an INVLPG instruction the TLB should not contain any translations for any part of the page frame associated with the designated logical address. Non-conformance. When the logical address designated by the INVLPG instruction is mappe
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 17 Deadlock May Occur in a Two-Processor System in the Presence of Probe to Memory- Mapped I/O Products Affected. A0, A2, A5 Normal Specified Operation. Processor should not hang. Non-conformance. In a multiprocessor system, if one processor (A) is continuously writing to a cacheable memory-mapped I/O block while the other processor (B) is trying to read the same cacheable I/O block, and at the same
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle Products Affected. A0, A2 Normal Specified Operation. The first processor cycle after a FID Change special cycle should be a Connect special cycle. Non-conformance. In rare circumstances, a processor victim write may be pending inside the processor when the FID Change special cycle is issued. Several bus clocks later, the WrVictimBl
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 19 Processor Does Not Support Reliable Microcode Patch Mechanism Products Affected. A5 Normal Specified Operation. The processor should function properly after a microcode patch is loaded. Non-conformance. The processor has the patch RAM BIST function disabled. Since BIST is not run on the patch RAM, reliable operation of the patch RAM cannot be guaranteed. Therefore it should not be used. Potential E
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 20 Processor Performance Counters Do Not Count Some x86 Instructions Products Affected. A0, A2, A5 Normal Specified Operation. The processor should count all x86 instructions when programmed to do so. Non-conformance. There are two types of uncounted instructions. One set of instructions is always uncounted. Another set of instructions are uncounted only if a certain data dependency exists. Instructio
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 21 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution Products Affected. A0, A2, A5 Normal Specified Operation. Self-modifying code sequences should be correctly detected and handled in a manner consistent with canonical results; stale code should not be executed. Non-conformance. The following scenario can result in a one-time execution of stale instructions: 1.
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 22 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation Products Affected. A0, A2, A5 Normal Specified Operation. Illegal values of ECX (that is, ECX>3) for the RDPMC (Read Performance Monitor Counter) instruction cause the processor to take a general protection exception. Non-conformance. If the RDPMC is executed in real mode with a specific illegal value of ECX=4, then the processor may
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 23 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults Products Affected. A0, A2, A5 Normal Specified Operation. Task gates should correctly use the TSS selector out of the task gate for CALL and JMP instructions. Non-conformance. When a task gate is used by a CALL or JMP instruction and any debug breakpoint is enabled through the DR7.LE or GE bits, the processor may, under certain ti
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 24 Single Step Across I/O SMI Skips One Debug Trap Products Affected. A0, A2, A5 Normal Specified Operation. When single stepping (with EFLAGS.TF) across an IN or OUT instruction that detects an SMI, the processor correctly defers taking the debug trap and instead enters SMM. Upon RSM (without I/O restart), the processor should immediately enter the debug trap handler. Non-conformance. Under this scen
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Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E— December 2002 2 Revision Determination Table 3 shows the AMD Athlon™ processor model 6 identification numbers returned by the CPUID instruction for each revision of the processor. Table 3. CPUID Values for the Revisions of the AMD Athlon™ Processor Model 6 Revision CPUID A0 660 A2 661 A5 662 16
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Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 3 Technical and Documentation Support The following documents provide additional information regarding the operation of the AMD Athlon™ processor model 6. Please refer to the data sheets listed in this section for product marking information. ■ AMD Athlon™ XP Processor Data Sheet: Processor Model 6, order #24309 ■ Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet, order #24319 ■ AMD Athlon™ MP
