Streszczenie treści zawartej na stronie nr. 1
Help Volume
© 1992-2002 Agilent Technologies. All rights reserved.
Agilent Technologies 16750A/B
Logic Analyzer
Streszczenie treści zawartej na stronie nr. 2
Agilent Technologies 16750A/B Logic Analyzer The Agilent Technologies 16750A/B 400 MHz State/2 GHz Timing Zoom logic analyzer offers 4M deep memory and very fast sample rates - up to 2 GHz for areas around the trigger - with up to 340 channels. “Getting Started” on • “Step 1. Connect the logic analyzer to the device under test” on page 13 page 11 “Step 2. Choose the sampling mode” on page 14 “Step 3. Format labels for the probed signals” on page 17 “Step 4. Define the trigger condition”
Streszczenie treści zawartej na stronie nr. 3
Agilent Technologies 16750A/B Logic Analyzer “Running Measurements” on page 86 “Displaying Captured Data” on page 88 “Using Symbols” on page 95 “Printing/Exporting Captured Data” on page 104 “Solving Logic Analysis Problems” on page 108 “Saving and Loading Logic Analyzer Configurations” on page 110 “Reference” on “The Sampling Tab” on page 115 page 113 “The Format Tab” on page 119 “The Trigger Tab” on page 146 “The Symbols Tab” on page 159 “Error Messages” on page 170 “
Streszczenie treści zawartej na stronie nr. 4
Agilent Technologies 16750A/B Logic Analyzer 4
Streszczenie treści zawartej na stronie nr. 5
Contents Agilent Technologies 16750A/B Logic Analyzer 1 Getting Started Step 1. Connect the logic analyzer to the device under test 13 Step 2. Choose the sampling mode 14 Step 3. Format labels for the probed signals 17 Step 4. Define the trigger condition 20 Step 5. Run the measurement 21 Step 6. Display the captured data 22 For More Information... 24 Example: Timing measurement on counter board 26 Example: State measurement on counter board 28 2Task Guide Probing the Device Under Test 33 Choosi
Streszczenie treści zawartej na stronie nr. 6
Contents To select transitional timing or store qualified 37 More on Store Qualification in Transitional Timing 38 More on Storing Transitions 38 Transitional Timing Considerations 39 Selecting the State Mode (Synchronous Sampling) 43 In Either Timing Mode or State Mode 52 Using 2 GHz Timing Zoom 54 Formatting Labels for Logic Analyzer Probes 57 To assign pods to one or two analyzers 57 To set pod threshold voltages 58 To assign probe channels to labels 59 To change the label polarity 61 To reor
Streszczenie treści zawartej na stronie nr. 7
Contents Using Symbols 95 To load object file symbols 96 To adjust symbol values for relocated code 97 To create user-defined symbols 98 To enter symbolic label values 99 To create an ASCII symbol file 100 To create a readers.ini file 101 Printing/Exporting Captured Data 104 Cross-Triggering 106 To cross-trigger between two analyzers 106 To cross-trigger with another instrument 107 Solving Logic Analysis Problems 108 To test the logic analyzer hardware 108 Saving and Loading Logic Analyzer Confi
Streszczenie treści zawartej na stronie nr. 8
Contents Importing Netlist and ASCII Files 121 Exporting ASCII Files 123 Importing ASCII Files 123 Termination Adapter 125 E5346A High Density Adapter 126 Mapping Connector Names 127 Import the Net List File 127 Verify Net to Label Mapping 128 Select/Create Interface Labels 129 Pod Assignment Dialog 130 Sampling Positions Dialog 131 The Trigger Tab 146 Trigger Functions Subtab 147 Settings Subtab 154 Overview Subtab 155 Default Storing Subtab 156 Status Subtab 157 Save/Recall Subtab 157 The Symb
Streszczenie treści zawartej na stronie nr. 9
Contents Error Messages 170 Must assign Pod 1 on the master card to specify actions for flags 171 Branch expression is too complex 171 Cannot specify range on label with clock bits that span pod pairs 176 Counter value checked as an event, but no increment action specified 177 Goto action specifies an undefined level 177 Maximum of 32 Channels Per Label 177 Hardware Initialization Failed 178 Must assign another pod pair to specify actions for flags 178 No more Edge/Glitch resources available for
Streszczenie treści zawartej na stronie nr. 10
Contents 4 Concepts Understanding Logic Analyzer Triggering 192 The Conveyor Belt Analogy 192 Summary of Triggering Capabilities 194 Sequence Levels 194 Boolean Expressions 197 Branches 198 Edges 198 Ranges 198 Flags 199 Occurrence Counters and Global Counters 199 Timers 200 Storage Qualification 201 Strategies for Setting Up Triggers 203 Conclusions 207 Understanding State Mode Sampling Positions 208 Glossary Index 10
Streszczenie treści zawartej na stronie nr. 11
1 Getting Started After you have connected the logic analyzer probes to your device under test (see “Step 1. Connect the logic analyzer to the device under test” on page 13), any measurement will have the following basic steps: 11
Streszczenie treści zawartej na stronie nr. 12
Chapter 1: Getting Started “Step 2. Choose the sampling mode” on page 14 “Step 3. Format labels for the probed signals” on page 17 “Step 4. Define the trigger condition” on page 20 “Step 5. Run the measurement” on page 21 “Step 6. Display the captured data” on page 22 If you have previously saved a logic analyzer setup to a configuration file, or if configuration files are included with an analysis probe, you can load the configuration file to set up the logic analyzer and define th
Streszczenie treści zawartej na stronie nr. 13
Chapter 1: Getting Started Step 1. Connect the logic analyzer to the device under test Step 1. Connect the logic analyzer to the device under test Before you begin setting up the logic analyzer for a measurement, you need to physically connect the logic analyzer to your device under test. There are several ways to connect logic analyzer probes to the device under test: Using the general-purpose probes, the standard flying lead set, and grabbers to connect to pins and leads in the device un
Streszczenie treści zawartej na stronie nr. 14
Chapter 1: Getting Started Step 2. Choose the sampling mode Step 2. Choose the sampling mode There are two logic analyzer sampling modes to choose from: timing mode and state mode. In timing mode, the logic analyzer samples asynchronously, based on an internal sampling clock signal. In state mode, the logic analyzer samples synchronously, based on a sampling clock signal (or signals) from the device under test. Typically, the signal used for sampling in state mode is a state machine or micr
Streszczenie treści zawartej na stronie nr. 15
Chapter 1: Getting Started Step 2. Choose the sampling mode If you chose Timing Mode 1. Select the timing analyzer full/half channel configuration. Typically, you can choose a half-channel configuration with faster sampling and greater memory depth, but with half of the channels. 2. Set the sample period. To capture signal level changes reliably, the sample period should be less than half (many engineers prefer one-fourth) of the period of the fastest signal you want to measure. If you chose
Streszczenie treści zawartej na stronie nr. 16
Chapter 1: Getting Started Step 2. Choose the sampling mode You can also specify clock input signal levels (from the device under test) that will enable (qualify) the sampling clock. In either sampling mode 1. Specify the trigger position. The trigger is the event in the device under test that you want to capture data around. Specify whether you want to look at data after the trigger (Start), before and after the trigger (Center), before the trigger (End), or use a percentage of the logic an
Streszczenie treści zawartej na stronie nr. 17
Chapter 1: Getting Started Step 3. Format labels for the probed signals Step 3. Format labels for the probed signals When a logic analyzer probes hundreds of signals in a device under test, you need to be able to give those channels more meaningful names than "pod 1, channel 1". The Format tab is mainly for assigning bus and signal names (from the device under test), to logic analyzer channels. These names are called labels. Labels are used when setting up triggers and displaying captured d
Streszczenie treści zawartej na stronie nr. 18
Chapter 1: Getting Started Step 3. Format labels for the probed signals To assign pods to one or two logic analyzers A logic analyzer's pod pairs can be assigned to one or two separate logic analyzers or they can be left unassigned. 1. In the Format tab, select the Pod Assignment button. 2. In the Pod Assignment dialog, drag a pod pair to the appropriate logic analyzer. 3. Select the Close button. To specify threshold voltages The threshold voltage is the voltage level that a signal must cross
Streszczenie treści zawartej na stronie nr. 19
Chapter 1: Getting Started Step 3. Format labels for the probed signals To assign names to logic analyzer channels 1. Select a label button, and either: Choose the Rename command, enter the label name, and select the OK button. Or, choose the Insert before or Insert after command, enter the label name, and select the OK button. 2. In the label row, select the button of the pod that contains the channels you want to assign. 3. Either choose one of the standard label assignments--dots (.) m
Streszczenie treści zawartej na stronie nr. 20
Chapter 1: Getting Started Step 4. Define the trigger condition Step 4. Define the trigger condition The trigger is the event in the device under test that you want to capture data around. 1. In the Trigger tab, and in the Trigger Functions subtab, choose the type of trigger you want to specify, and select the Replace button. 2. In the Trigger Sequence portion of the Trigger tab, select the buttons to define the label values and/or other conditions you want to trigger on. Next: “Step 5. Run t
