Streszczenie treści zawartej na stronie nr. 1
KD-SH99R
SERVICE MANUAL
CD RECEIVER
KD-SH99R
ATT
ANGLE
EQ
CD
FM
AM R D
CH
AUX SEL
VOLUME
RM-RK100
Area Suffix
E ------- Continental Europe
EX ----- Central Europe
Contents
Safety precaution 1- 2
Preventing static electricity 1- 3
Disassembly method 1- 4
Adjustment method 1-15
Flow unit reading TOC
of CD/CD-R/CD-RW
1-18
Maintenance of laser pickup
1-20
Replacement of laser pickup
1-20
Description of major ICs
1-21~45
No.49645
COPYRIGHT 2001 VICTOR COMPANY OF JA
Streszczenie treści zawartej na stronie nr. 2
KD-SH99R < Service mode > The menu in the service mode can be switched with UP/DOWN. The menu selected by the SEL button input is executed. The ordinary mode "UP" + "DOWN" + VR counterclockwise rotation. DEL EEPROM EEPROM data all clear (changer is connected). CH CH ERR CD changer error career call (changer is connected). DELL CH ERR CD changer EEPROM clear (EEPROM career) RUNNING CD CD running mode (Do not use in service). RUNNING SH Running mode of front panel (Do not use in service). DEL DATA
Streszczenie treści zawartej na stronie nr. 3
KD-SH99R Memory to EEPROM of 6 digits, 1st and 2nd digit are indicate the operation mode when occur the error, 3rd to 6th digit are indicate details of error. LCD indication time is use lower 2digits of details of error. This series is indicate ERR XX (XX is error code). When details of error is 0A0001 , it is indicate ERR 01, details of error is 0E0031 , it is ERR 31. Switch is from this side sequentially PSW1, PSW2,.....PSW6. Details of error Error code
Streszczenie treści zawartej na stronie nr. 4
KD-SH99R Description of major ICs UPD784215AGC146(IC701):MAIN CPU 1.Pin layout 75 51 76 50 100 26 125 2.Block diagram INTP2/NMI RxD1/SI1 PROGRAMMABEL UART/IOE1 TxD1/SO1 INTP0,INTP1 INTERRUPT BAUD-RATE ASCK1/SCK1 INTP3-INTP6 CONTROLLER GENERATOR RxD2/SI2 TI00 UART/IOE2 TIMER/COUNTER TxD2/SO2 TI01 BAUD-RATE (16 BITS) ASCK2/SCK2 TO0 GENERATOR CLOCKED SI0 TI1 TIMER/COUNTER1 SERIAL SO0 TO1 (8 BITS) INTERFACE SCK0 TIMER/COUNTER2 AD0-AD7 TI2 (8 BITS) TO2 A0-A7 A8-A15 TIMER/COUNTER5 TI5/TO5 BUS I/F (8
Streszczenie treści zawartej na stronie nr. 5
KD-SH99R UPD784215AGC146(1/2) Pin No. Symbol I/O Function 1 PREQ O Mechanism power supply ON/OFFdemand output("L":On demand) 2 AMUTE O Audio output MUTE control signal output ("L" :MUTE ON) 3 O Non connected 4 O Non connected 5 O Non connected 6 O Non connected 7 DIMMER-OUT O Unused output port 8 ANT PEM O Antenna remote output 9 VDD - 5V connection 10 X2 Sub-clock 32.738MHz 11 X1 I Sub-clock 32.738MHz 12 VSS - GND connection 13 XT2 Sub-clock 12.5MHz 14 XT1 I Sub-clock 12.5MHz 15 RESET Reset de
Streszczenie treści zawartej na stronie nr. 6
KD-SH99R UPD784215AGC146(2/2) Pin No. Symbol I/O Function 51 O Non connected 52 O Non connected 53 O Non connected 54 I The detach signal input. It is L of 200ms or more and operation mode. DETACH It is H and POWER SAVE. 55 O Signal output for VCR control VCR CONT 56 I Panel position detection switch one signal input. PNL SW1 57 I Panel position detection switch two signal input. PNL SW2 58 I Panel position detection switch three signal input. PNL SW3 59 I Panel position detection switch four s
Streszczenie treści zawartej na stronie nr. 7
KD-SH99R UPD63711AGC(IC603):RF Servo amp 1.Pin layout 144 109 1 108 36 73 37 72 2.Pin function UPD63711AGC(1/3) Pin No. Symbol I/O Function 1 VSSO - It is GND of the logic circuit. 2 ZRASO O It is RFOK signal output terminal. 3 ZCASO I Reset signal input terminal. (Active row) 4 ZCAS1 I Command/parameter identification signal input terminal A0=L:STB active=Address register set. A0=H:STB active= Parameter set. 5 VSSO I The data strove signal input terminal. It is signal to de the latch i
Streszczenie treści zawartej na stronie nr. 8
KD-SH99R UPD63711AGC(2/3) Pin No. Symbol I/O Function 33 I LRCK signal input terminal to building DAC into. IO11 34 O Signal which distinguishes left channel/right channel of voice data output IO12 from DOUT. 35 O Terminal (88.2kHz)(WDCK)of the output of the frequency signal twice IO13 defect detection output terminal(HOLD) LRCK HOLD/WDCK can be switched with the microcomputer. 36 O Terminal of output of data of Digital audio interface. VSSO 37 - It is GND of the logic circuit. VDD1 38 O Buffe
Streszczenie treści zawartej na stronie nr. 9
KD-SH99R UPD63711AGC(2/2) Pin No. Symbol I/O Function 78 - Equalizer part connection terminal of RF amplifier. EQ2 79 EQ1 80 I Reversing input terminal of RF saming amplifier. RF 81 - It is GND of an analog circuit. AGND 82 I Photo detector A input terminal. A 83 I Photo detector B input terminal. C 84 I Photo detector C input terminal. B 85 I Photo detector D input terminal. D 86 I Photo detector F input terminal. F 87 I Photo detector E input terminal. E 88 - Positive power supply supply termi
Streszczenie treści zawartej na stronie nr. 10
KD-SH99R UPD70F3033AC015(IC606):SUB CPU 1.Pin layout 100 76 1 75 25 51 26 50 2.Pin function UPD70F3033AC015(1/2) Pin No. Symbol I/O Function 1 TSI O CD TEXT control parameter cereal output. 2 TSCK O CD TEXT control cereal clock output. 3 JBSO O JBUS cereal data output. 4 JBSI I JBUS cereal data input. 5 JBCK I/O Cereal clock I/O. 6 EVDD - 5V(power supply for port for I/O). 7 EVSS - GND(GND for port for I/O). 8 TSTB O CD TEXT parameter strobe signal output. 9 XRESET O LSI reset output. 10
Streszczenie treści zawartej na stronie nr. 11
KD-SH99R UPD70F3033AC015(2/2) Pin No. Symbol I/O Function 51 AD4 I/O DECODER I/O data bus. 52 AD5 I/O DECODER I/O data bus. 53 AD6 I/O DECODER I/O data bus. 54 AD7 I/O DECODER I/O data bus. 55 BVDD - 5V 56 BVSS - GND 57 --- O (Non connected) 58 --- O (Non connected) 59 --- O (Non connected) 60 --- O (Non connected) 61 --- O (Non connected) 62 --- O (Non connected) 63 --- O (Non connected) 64 --- O (Non connected) 65 MD O DAC mode control data. 66 MC O DAV mode control clock. 67 ML O DAC mode con
Streszczenie treści zawartej na stronie nr. 12
KD-SH99R MAS3507D-QG-G10 (IC806) :MP3 decoder 1.Pin layout 33 32 31 30 29 28 27 26 25 24 23 34 PI3 22 PI13 PI2 35 21 PI14 PI1 36 20 PI15 PI0 37 19 PI16 CLKO 38 18 PI17 PUP 39 17 PI18 WSEN 40 16 PI19 WRDY 41 15 RCS AVDD 42 14 PR CLKI 43 13 VSENS AVSS 44 12 DCSO 1 23 4 5 6 7891011 (TOP VIEW) 2.Block diagram MPEG Bit Stream Ancillary Sync Data to C Volume Digital Audio Output Decoder MPEG Tone Status Decoder Control Config.Reg. PIO Status Start-up Config. 1-29 TE PI4 POR SIC SII I2CC SID I2CD XVSS
Streszczenie treści zawartej na stronie nr. 13
KD-SH99R 3.Pin function MAS3507D-QG-G10(1/2) Pin no. Symbol I/O Function 1 TE I Test Enable 2 POR I Reset, Active Low 2 3 I2CC I/O I C Clock Line 2 4 I2CD I/O I C Data Line 5 VDD Supply Positive Supply for Digital Parts 6 VSS Supply Ground Supply for Digital Parts 7 DCEN I Enable DC/DC Converter or Voltage Supervision 8 EOD OUT PIO End of DMA, Active Low 9 RTR OUT PIO Ready to Read, Active Low 10 RTW OUT PIO Ready to Write, Active Low 11 DCSG Supply DC Converter Transistor Ground 12 DCSO O DC
Streszczenie treści zawartej na stronie nr. 14
KD-SH99R 3.Pin function MAS3507D-QG-G10(2/2) Pin no. Symbol I/O Function 1) 2 36 PI1 IN/OUT Start-up : SDO Select 32 bit mode / 16 bit I S mode Operation : MPEG header bit 30(Emphasis) 1) 37 P0 IN/OUT Start-up : Select Multimedia mode / Broadcast mode Operation MPEG header bit 31 (Emphasis) 38 CLKO O Clock Output (normal 24.576 MHz) 39 PUP O Power Up, i.e.Status of Voltage Supervision 40 WSEN I WS Enable : Enable DSP 41 ERDY O WSEN=0 : Valid clock input at CLKI WSEN=1 : Clock synthesizer
Streszczenie treści zawartej na stronie nr. 15
KD-SH99R LC895199K-ND2(IC601):CD-ROM decoder 1.Pin layout 144 109 1 108 36 73 37 72 2.Pin function LC895199K-ND2(1/3) Pin No. Symbol Function 1 VSSO 2 ZRASO RAS signal output terminal to buffer DRAM 3 ZCASO CAS signal output 0 terminal to buffer DRAM(0 is used usually) 4 ZCAS1 CAS signal output terminal 1 to buffer DRAM 5 VSSO 6 ZOE Buffer DRAM output enable 7 ZUWE Buffer DRAM upper write enable 8 ZLWE Buffer DRAM lower write enable 9 VSSO 10 RA0 Address signal output terminal to data b
Streszczenie treści zawartej na stronie nr. 16
KD-SH99R LC895199K-ND2(2/3) Pin No. Symbol Function 51 TEST0 The terminal TEST.Please connect with VSS 52 XTALCK X'tal oscillation circuit input terminal 53 XTAL X'tal oscillation circuit output terminal 54 VDD0 5.0V 55 VSS0 56 MCK 1/1,2/2,STOP output terminal of XTALCK 57 TEST1 The terminal TEST. Please connet with VSS 58 DSDATA DAC output terminal 59 DLRCK 60 DBCK 61 C2PO Terminal for CD-DSP I/F 62 SDATA 63 BCK 64 LRCK 65 EXCK SUB-CODE I/O terminal 66 WFCK 67 SBSO 68 SCOR 69 PLL1 Relation co
Streszczenie treści zawartej na stronie nr. 17
KD-SH99R LC895199K-ND2(3/3) Pin No. Symbol Function 110 DAO ATAPI data bus 111 ZPDIAG 112 DA1 113 ZIOCS16 114 HITRQ 115 ZDMACK 116 VSS1 117 IORDY ATAPI data bus 118 ZDIOR 119 ZDIOR 120 DMARQ 121 VSS1 122 DD15 ATAPi data bus 123 DDO ATAPi control signal 124 DD14 ATAPI control signal 125 DD1 126 VDDO 5.0V 127 VSS1 128 DD13 ATAPI control signal 129 DD2 130 DD12 131 DD3 132 VSS1 133 DD11 ATAPI control signal 134 DD4 135 DD10 136 VSS1 137 VDD0 5.0V 138 DD5 ATAPI control signal 139 DD9 140 DD6 141 VSS
Streszczenie treści zawartej na stronie nr. 18
KD-SH99R HA13164 (IC961) : Regulator 1.Pin layout 12 34 56 78 9101112131415 2.Block diagram +B C1 C2 100u 0.1u ACC VCC ACC 8 3 BATT.DET OUT 9 ANT OUT Surge Protector 2 C3 0.1u EXT OUT COMPOUT 1 BIAS TSD 6 C4 0.1u VDD OUT ANT CTRL 4 7 C7 0.1u CTRL 11 SW5VOUT 5 CD OUT 12 C5 0.1u ILMOUT AUDIO OUT 10 14 C8 C6 0.1u 10u 15 13 R1 GND ILM AJ UNIT R: C:F note1) TAB (header of IC) connected to GND 3.Pin function Pin No. Symbol Function 1 EXT Output voltage is VCC-1 V when M or H level appl
Streszczenie treści zawartej na stronie nr. 19
KD-SH99R LC75878W (IC501) : LCD driver 1. Pin layout 100 ~ 76 1 75 ~ ~ 25 51 26 ~ 50 2. Block diagram GENERAL COMMON SEGMENT DRIVER & LATCH DRIVER PORT CONTROL CLOCK OSC REGISTER GENERATOR VLCD CONTRAST SHIFT REGISTER ADJUSTER VLCD0 VLCD1 CCB VLCD2 INTERFACE VLCD3 VLCD4 VDD VSS 3. Pin function No. Symbol I/O Function 1~73 SEG1~SEG73 O Segment driver output pin. 74 SEG74 O Segment driver output pin. 75 SEG75 O Segment driver output pin. 76~83 COM8~COM1 O Common driver output pin. 84~87 P1
Streszczenie treści zawartej na stronie nr. 20
12dB 12dB KD-SH99R M61508FP-X (IC911) : E. volume 1. Pin layout & Block diagram 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 50K LOUDNESS + VDO VCC (Digital) (Anarog) 3BAND TONE CONTROL (BASS/MID/TREBLE) Soft select ZERO CROSS A DETECTOR B Zero detect I/F REF Select SW ZERO CROSS B DETECTOR A TIMER DETECTOR LOUDNESS + 3BAND TONE CONTROL GND (BASS/MID/TREBLE) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2. Pin function Pin No. Symbol Function 1 REF Grand for IC signal 2 DEFP IN1
