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Application Note: Embedded Processing
R
Reference System: OPB IIC Using the
ML403 Evaluation Platform
Author: Paul Glover, Ed Meinelt, Lester Sanders
XAPP979 (v1.0) February 26, 2007
Summary This application note describes how to build a reference system for the On-Chip Peripheral Bus
Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded
system in the ML403 Embedded Development Platform. The reference system is Base System
Builder (BSB) based.
An IIC primer is give
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R Introduction Introduction This application note accompanies a reference system built on the ML403 development board. Figure 1 is a block diagram of the reference system. OPB OPB UART OPB INTC 16550 IIC OPB PowerPC™ PLB 405 Processor PLB PLB DDR BRAM X979_01_022307 Figure 1: OPB IIC Reference System Block Diagram The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB IIC core. IIC Primer Figure 2 shows components on an IIC bus.Two IIC masters and three IIC slaves are shown
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R Introduction Figure 4 shows the format of the data transfer of two bytes on the IIC bus, beginning with the START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus. After a START condition, an eight bit field is transmitted containing a 7 bit address and a single Read/Write (R/W) bit. This 8 bit address/direction field is followed by an Acknowledge bit. After the address/data field, an eight bit data field is followed by an acknowledge bit (A). The last 8- bit da
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R Reference System Specifics Figure 6 shows the acknowledge bit on the IIC bus. Data output by transmitter Not acknowledge Data output by receiver Acknowledge SCL from master 12 8 9 S Clock pulse for START acknowledgment condition X979_06_012907 Figure 6: Acknowledge on the IIC Bus Figure 7 shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters monitor the IIC bus to determine if the bus is active. The bus is inactive when SCL and SDA are high for a bus free period tBUF
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R Reference System Specifics ML403 XC4VFX12 Address Map Table 1: ML403 XC4VSX12 System Address Map Peripheral Instance Base Address High Address PLB_DDR DDR_SDRAM_32Mx64 0x00000000 0x03FFFFFF OPB UART16550 RS232_Uart_1 0x40400000 0x4040FFFF OPB INTC opb_intc_0 0x41200000 0x4120FFFF PLB BRAM plb_bram_if_cntlr_0 0xFFFF8000 0xFFFFFFFF OPB IIC IIC_EEPROM 0x40800000 0x4080FFFF OPB IIC Registers Table 2 provides the register map for the OPB IIC core. Table 2: OPB IIC Registers Register Address Device
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R Reference System Specifics Table 3: OPB IIC Control Register (Contd) Bit(s) Name Description Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA line during acknowledge cycles for both Master and Slave receivers. Because Master receivers indicate the end of data reception by not 27 TXAK acknowledging the last byte of the transfer, this bit is used to end a Master receiver transfer. As a slave, this bit must be set prior to receiving the byte to no acknowledge. Transmit
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R Reference System Specifics Table 4: Status Register Bit Definitions (Contd) Bit(s) Name Description 30 AAS Addressed as Slave. When the address on the IIC bus matches the Slave address in the Address Register (ADR), the IIC Bus Interface is being addressed as a Slave and switches to Slave mode. If 10-bit addressing is selected this device will only respond to a 10-bit address or general call if enabled. This bit is cleared when a stop condition is detected or a repeated start occurs. 31 ABGC Ad
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R Reference System Specifics Configuring the OPB IIC Core Figure 8 shows how to specify the values of IIC generics in EDK. To access the dialog box in the figure, double click on the OPB IIC core in the EDK System Assembly View.. X979_08_012907 Figure 8: Specifying the Values of OPB IIC Generics in EDK Microchip 24LC04 The Microchip Technology 24LC04B-I/ST with 4-KB EEPROM is provided on the ML403 board to store non-volatile data. The EEPROM write protect is tied off on the board to disable its har
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R ML403 Board Information is ‘1010 for read and write operations. The A2, A1 bits are dont cares. The A0 bit is used by the master device to select which of the two 256-word blocks of memory are accessed. The 24LC04 write transactions are either a byte write or a page write. The page write begins the same as the byte write but instead of generating a stop condition the master transmits up to 16 data bytes to the 24LC04B. The 24LC04 supports current address, random, and sequential read operations
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R ML403 Board Information The resistors are located on the board as shown in Figure 12. X979_12_022307 Figure 12: ML40x Resistors XAPP979 (v1.0) February 26, 2007 www.xilinx.com 10
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R ML403 Board Information If additional IIC devices are connected to the bus via the expansion header as shown in Figure 13, insert additional pull-up resistors on the external signals connected at pins 31 and 32. The resistor values are dependent on the voltage. HDR 1 X 32 1 2 3 4 5 NC 6 7 8 9 10 NC 11 FPGA_PROM_CPLD_TMS 12 FPGA_PROM_CPLD_TCK 13 EXPANSION_TDO 14 CPLD_TDO 15 GPIO_LED_N 16 GPIO_SW_N 17 GPIO_LED_C 18 GPIO_SW_C 19 GPIO_LED_W 20 GPIO_SW_W 21 GPIO_LED_S 22 GPIO_SW_S 23 GPIO_LED_E 24
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R ML403 Board Information Figure 14 shows the FPGA pins driving the IIC Bus. C12 SMA_DIFF_CLK_IN_N IO_L8N_GC_LC_3_C12 C13 SMA_DIFF_CLK_IN_P IO_L8P_GC_LC_3_C13 A17 IIC_SCL IO_L7N_GC_LC_3_A17 B17 IIC_SDA IO_L7P_GC_LC_3_B17 B10 DDR_CLK1_N IO_L6N_GC_LC_3_B10 A10 DDR_CLK1_P IO_L6P_GC_LC_3_A10 A15 DDR_A13 IO_L5N_GC_LC_3_A15 A16 DDR_BA1 IO_L5P_GC_LC_3_A16 B12 DDR_BA0 IO_L4N_GC_VREF_LC_3_B12 B13 DDR_CLK_P IO_L4P_GC_LC_3_B13 C14 MOUSE_DATA IO_L3N_GC_LC_3_C14 C15 PHY_TXCLK IO_L3P_GC_LC_3_C15 A11 GPIO_LED_
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R ML403 Board Information Figure 15 shows the Aardvark Control Center GUI. X979_15_012907 Figure 15: Aardvark Control Center Interfacing to the OPB IIC on the ML403 Board to the Aardvark Adapter Figure 16 shows the principle interface blocks when transferring data between the OPB IIC in the XC4VFX12 on the ML403 board and the IIC in the Aardvark Adapter. ML403 - XCVFX12 DDR PC PPC OPB IIC Aardvark USB Adaptor BRAM X979_16_012907 Figure 16: Interfacing ML403 Board OPB IIC with the Aardvark Adapte
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R ML403 Board Information 3. Invoke XMD and connect to the MicroBlaze processor by the following command: xmd -opt xapp.opt 4. Download the executable by the following command dow /executable.elf Executing the Reference System from EDK To execute the system using EDK, follow these steps: 1. Opensystem.xmp inside EDK. 2. Use Hardware → Generate Bitstream to generate a bitstream 3. Download the bitstream to the board using Device Configuration → Download Bitstream. 4. Invoke XMD with Debug La
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R ML403 Board Information low_level_dynamic_eeprom: This project transmits and receives data using the low level (L0) software driver. The OPB IIC is the master and the 24LC04 is configured as the slave. The OPB IIC master writes data into the 24LC04 and reads it back. This is a polled mode example.c Projects interfacing to Aardvark Adapter multi_master: This project transmits and receives data using the high level (L1) software driver. The OPB IIC is an IIC master and the IIC in the Aardvark is
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R Running the Applications Figure 18 shows the slave example. The message is in transmit.txt, and is the sentence "Lester was here.". The transaction log matches the message. The address is 0x70. Click Master Write to generate the transaction. X979 18 012907 Figure 18: Slave Example Running the In XPS, select the Applications tab under the Project Information Area to view the Software Project. Applications Figure 19 shows the structure of thedynamic_eeprom project. Make the dynamic_eeprom projec
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R Running the Applications Select dynamic_eeprom and right click to build the project. If more than one software project is used, make the unused software projects inactive. Connect a serial cable to the RS232C port on the ML403 board. Start up a HyperTerminal. Set Bits per second to 9600, Data bits to 8, Parity to None, and Flow Control to None, as shown in Figure 20. X979_20_012907 Figure 20: HyperTerminal Parameters From XPS, start XMD and enterrst. Invoke GDB and select Run to start the appl
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R Using ChipScope with OPB IIC Using To facilitate the use of ChipScope to analyze OPB IIC hardware, theiic.cdc file is included in theml403_ppc_opb_iic/chipscope directory. Theiic.cdc is used to insert a ChipScope with ChipScope ILA core into the opb_iic core. The following steps are used to insert a core and OPB IIC analyze OPB IIC problems with ChipScope. 1. Invoke XPS. Run Hardware → Generate Netlist. 2. In theiic.cdc file, change the path name to the directory in which the d
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R Using ChipScope with OPB IIC 5. Figure 23 shows the GUI for making net connections. Click Next to move to theModify Connections window. If there are any red data or trigger signals, correct them. The Filter Pattern can be used to find net(s). As an example of using the Filter Pattern, enterintr in the dialog box to locate interrupt signals. In the Net Selections area, select either Clock, Trigger, or Data Signals. Select the net and click Make Connections. X979_23_012907 Figure 23: Making Net C
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R Using ChipScope with OPB IIC The waveform viewer is more readable when buses rather than discrete signals are displayed. The Reverse Bus Order operation below Add to Bus in the figure can be useful in analyzing ChipScope results. X979_24_022307 Figure 24: Setting Up the Chipscope Trigger 11. Set the trigger in the Trigger Setup window. The trigger used depends on the problem being debugged. Change the Windows to N samples to a setting of 100. Arm the trigger by selecting Trigger Setup → Arm, or
