Streszczenie treści zawartej na stronie nr. 1
DSP96002
32-BIT
DIGITAL SIGNAL PROCESSOR
USER’S MANUAL
Motorola, Inc.
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive, West
Austin, Texas 78735-8598
Streszczenie treści zawartej na stronie nr. 2
SECTION 1 DSP96002 INTRODUCTION This manual describes the first member of a family of dual-port IEEE floating point programmable CMOS processors. The family concept defines a core as the Data ALU, Address Generation Unit, Program Con- troller and associated Instruction Set. The On-Chip Program Memory, Data Memories and Peripherals sup- port many numerically intensive applications and minimize system size and power dissipation; however, they are not considered part of the core. The firs
Streszczenie treści zawartej na stronie nr. 3
1 - 2 DSP96002 USER’S MANUAL MOTOROLA
Streszczenie treści zawartej na stronie nr. 4
SECTION 2 SIGNAL DESCRIPTION AND BUS OPERATION 2.1 PINOUT The functional signal groups of the DSP96002 are shown in Figure 2-2, and are described in the following sections. A pin allocation summary is shown in Figure 2-1. Specific pinout and timing information is avail- able in the DSP96002 Technical Data Sheet (DSP96002/D). 2.1.1 Package The DSP96002 is available in a 223 pin PGA package. There are 176 signal pins (including 5 spares), 17 power pins and 30 ground pins. All pack
Streszczenie treści zawartej na stronie nr. 5
CPU Pins Pins Reset and IRQs 4 Clock Input 1 OnCE Port 4 CPU Spare 1 Quiet Power 4 Quiet Ground 4 CPU Subtotal 18 Power/Ground Planes Pins Package Noisy Power Plane 2 Package Noisy Ground Plane 5 Package Quiet Power Plane 1 Package Quiet Ground Plane 1 Power/Ground Plane Subtotal 9 Each Port Both Ports Port A/B Pins Pins Data Bus 32 64 Address Bus 32 64 Data Power 2 4 Data Ground 4 8 Address Power 2 4 Address Ground 4 8 Addr/Data Subtotal 76 152 Each Port Both Ports
Streszczenie treści zawartej na stronie nr. 6
ADDRESS BUS A 32 32 ADDRESS BUS B aA0-aA31 bA0-bA31 V (2) (2) V cc cc V (4) (4) V ss ss DATA BUS A 32 32 DATA BUS B aD0-aD31 bD0-bD31 V (2) (2) V cc cc V (4) (4) V ss ss PORT A BUS CONTROL PORT B BUS CONTROL aS1 bS1 aS0 bS0 — — aR/ W bR/ W DSP96002 — – — – a B S B S — – — – a B L b B L 223 PINS — – — – a T T b T T — – — – a T S b T S — – — – a T A b T A — – — – a A E b A
Streszczenie treści zawartej na stronie nr. 7
ing hardware reset and becomes a level sensitive or negative edge triggered, maskable interrupt request input during normal instruction processing. MODA, MODB and MODC select one of 8 initial chip operating modes, latched into the operating mode register — — — — – — — — – (OMR) when the R E S E T pin is deasserted. If I R Q C is asserted syn- chronous to the input clock (CLK), multiple processors can be resynchronized using the — — — – WAIT instruction and asserting I R Q C to exit
Streszczenie treści zawartej na stronie nr. 8
Bus Control VCC(2) (Power) - isolated power for the bus control I/O drivers. Must be tied to all other chip power pins externally. User must provide adequate external decoupling capacitors. Bus Control VSS(4) (Ground) - isolated ground for the bus control I/O drivers. Must be tied to all oth- er chip ground pins externally. User must provide adequate external decoupling capac- itors. 2.1.4 On-chip Emulator Interface (OnCE) (4 Pins) — – D R (Debug Request) - The debug enab
Streszczenie treści zawartej na stronie nr. 9
— – and may change only when T S is deasserted. A0-A31 are three-stated during hard- ware reset. D0-D31 (Data Bus) - three-state, active high, bidirectional input/outputs when a bus master or — – not a bus master. The Data Enable ( D E) input acts as an output enable control for D0-D31. As a bus master, the data lines are controlled by the CPU instruction execution or the DMA controller. D0-D31 are also the Host Interface data lines. If there is no ex- ternal bus activity, D
Streszczenie treści zawartej na stronie nr. 10
— an "early write" signal for DRAM interfacing. R/ W is high for a read access and is low — for a write access. The R/ W pin is also the Host Interface read/write input. As an in- — — put, R/ W may change asynchronous relative to the input clock. R/ W goes high if — the external bus is not used during an instruction cycle. R/ W is three-stated during hardware reset. — – B S (Bus Strobe) - three-state, active low output when a bus master, three-stated when not a bus master. Assert
Streszczenie treści zawartej na stronie nr. 11
— – — – When a bus master, the combination of B S and T S can be decoded externally to determine the status of the current bus cycle and to generate hardware strobes useful for latching address and data signals. The encoding is shown in Figure 2-4. WS WS t0 t1 t2 t3 t0 t1 t2 tw t2 tw t2 t3 CLK — – B — – T S — – A — – D — – — – B S T S Bus Status Strobe Generation Application 1 1 Idle — – 0 1 Cycle Start Address Strobe ( A S) 0 0 Wait — – 1 0 Cycle End Data Strobe ( D S) Figure 2-4. B
Streszczenie treści zawartej na stronie nr. 12
— – A E (Address Enable) - active low input, must be asserted and deasserted synchronous to — – the input clock (CLK) for proper operation. If a bus master, A E is asserted to enable — – the A0-A31 address output drivers. If A E is deasserted, the address output drivers are three-stated. If not a bus master, the address output drivers are three-stated regard- — – — – less of whether A E is asserted or deasserted. The function of A E is to allow mul- tiplexed bus systems to
Streszczenie treści zawartej na stronie nr. 13
register (IVR) onto the data bus outputs D0-D31. This provides an interrupt acknowl- edge capability compatible with MC68000 family processors. — – If the host interface is in DMA mode, H A is used as a DMA transfer acknowledge in- put and it is asserted by an external device to transfer data between the Host Interface — – registers and an external device. In DMA read mode, H A is asserted to read the Host — – Interface RX register on the data bus outputs D0-D31. In DMA write mode, H A i
Streszczenie treści zawartej na stronie nr. 14
(BSET, BCLR, BCHG) will not give up bus mastership until the end of the current instruc- —— – tion. B G is ignored during hardware reset. — – — – B A (Bus Acknowledge) - Open drain, active low output. When deasserting B A, the — – DSP96002 drives B A high during half a CLK cycle and then disables the active pull- — up. In this way, only a weak external pull-up resistor is required to hold the line high. – — – B A may be directly connected to B B in order to obtain the same functionalit
Streszczenie treści zawartej na stronie nr. 15
— – B L (Bus Lock) - active low output, never three-stated. Asserted at the start of an external indivisible Read-Modify-Write (RMW) bus cycle (providing an "early bus start" signal for — – DRAM interfacing) and deasserted at the end of the write bus cycle. B L remains as- — – serted between the read and write bus cycles of the RMW bus sequence. B L can be used to indicate that special memory timing (such as RMW timing for DRAMs) may be used or to "resource lock" an external mu
Streszczenie treści zawartej na stronie nr. 16
3:4. When the Address and Memory Reference signals are stable, the data transfer is enabled by — – — – the Transfer Strobe T S signal. T S is asserted to "qualify" the Address and Memory — – Reference signals as stable and to perform the read or write data transfer. T S is asserted in the second phase of the bus cycle. — – 3:5. Wait states are inserted into the bus cycle controlled by a wait state counter or by T A, whichever is longer. The wait state counter is loaded from
Streszczenie treści zawartej na stronie nr. 17
— – The disadvantage of this technique is that access time is measured from T S instead of from the address — – or B S. Hence faster memories are required. DSP96002 STATIC RAM — — — R/ — – O — – S1 or S0 C — – Figure 2-6. W E Controlled Writes Interface To Static RAM — – 3. 6.1.2 W E Controlled Writes — – This form of static interface uses the memory write enable ( W E) as the write strobe. The DSP96002 — — – R/ W signal is used to form a late read/write indication by gati
Streszczenie treści zawartej na stronie nr. 18
The Port A/B bus control signals are designed for efficient interface to DRAM/VRAM devices in both ran- dom read/write cycles and fast access modes such as those listed above. The bus control signal timing is specified relative to the external clock (CLK) to enable synchronous control by an external state ma- — – chine. An on-chip page circuit controls the T T pin, indicating to the external state machine when a slow or fast access is being made. The page circuit operation and pro
Streszczenie treści zawartej na stronie nr. 19
4.11.2 The Arbitration Protocol The bus is arbitrated by a central bus arbitrator, using individual request/grant lines to each bus master. The arbitration protocol can operate in parallel with bus transfer activity so that the bus hand-over can be made without much performance penalty. The arbitration sequence occurs as follows: — – 5:12. All candidates for bus ownership assert their respective B R signals as soon as they need the bus. — – 5:13. The arbitration logic designate
Streszczenie treści zawartej na stronie nr. 20
— – An implementation of a bus arbitration scheme may hold B G asserted, for example, to the current bus owner if none of the other devices are requesting the bus. As a consequence, the current bus master may — – — – keep B A asserted after ceasing bus activity, regardless of whether B R is asserted or deasserted. This situation is called "bus parking" and allows the current bus master to use the bus repeatedly without re-arbitration until some other device requests the bus.
