Streszczenie treści zawartej na stronie nr. 1
NEC Enterprise Server
NEC Express5800/1000 Series
NEC Express5800/1000 Technology Guide Vol.1
® ®
Powered by the Dual-Core Intel Itanium Processor
NEC Express5800/1000 Series
Reliability and Performance through
3
the fusion of the NEC “A ” chipset and
® ®
the Dual-Core Intel Itanium processor
1320Xf/1160Xf 1080Rf
Streszczenie treści zawartej na stronie nr. 2
In today’s fast-paced business environment, all enterprises, from the world’s largest companies to the smallest depend on IT. Enterprise resource planning (ERP), customer relationship management (CRM), and business intelligence (BI ) all require that transactions are quickly processed and that the resulting data is reliable as to meet the requirements of the rapidly changing business environment. The need for higher performance and better reliability is growing exponentially in enterprise I
Streszczenie treści zawartej na stronie nr. 3
Cell Cell Cell n Internal Connections of the n System Hardware Layout of the Express5800/1000 Express5800/1000 Series Series Server (1320Xf) Increased inter-Cell data transfer speeds Fan box Cell Service Crossbar Cell card 1 Processor * card * R edundant configuration available 1 Clock card * Fan box HDD Bay PCI box PCI slots * R edundant configuration available Processor Power Power Bay Distribution Unit (PDU) Cell Controller Processor 2 Hot Pluggable * Service Processor Fan box Proc
Streszczenie treści zawartej na stronie nr. 4
Supercomputer-class Performance Features for performance improvement ® ® Dual-Core Intel Itanium processor and high-speed inter/intra Cell cache-to-cache data transfer At the heart of the Express5800/1000 series server is the ® ® 64-bit Dual-Core Intel Itanium processor, redesigned for Increased Memory Bandwidth Improved Inter/Intra-Cell memory data transfer even faster processing of larger data sets. The system has been equipped with the NEC designed chipset, Very Large Cache (VLC) A
Streszczenie treści zawartej na stronie nr. 5
VLC Architecture High-speed / low latency Intra-Cell cache-to-cache data transfer The Express5800/1000 series server Very Large Cache (VLC) Architecture Split BUS Architecture Higher cache memory implements the VLC architecture, which access latency. Increased enterprise CPU CPU CPU CPU CPU CPU CPU CPU Non-uniform applications allows for low latency cache-to-cache Cache Cache Cache Cache Cache Cache Cache Cache cache-to-cache data Memory Memory Memory Memory Memory Memory Memory Memory pe
Streszczenie treści zawartej na stronie nr. 6
Mainframe-class RAS Features RAS Design Philosophy Realization of a mainframe-class continuous operation through the pursuit of reliability and availability in a single server construct Generally, in order to achieve reliability and availability on an Continuous operations throughout failures; minimize the open server, clustering would be implemented. However, spread of failures; and smooth recovery after failures were clustering comes with a price tag. To keep costs at a minimum, goals
Streszczenie treści zawartej na stronie nr. 7
Memory Mirroring Continuous operation even in the event of a non-correctable memory error The Express5800/1000 series server supports high-level memory RAS features to ensure that the server can rapidly detect memory CPUCPU CPU CPU errors, reduce multi-bit errors and continually operate even in Memory the event of memory chip or memory controller failures. Memory Image scan, memory chip sparing (SDDC*) and memory scrubbing are Cell Memory Memory examples of those features. I/F Controller Co
Streszczenie treści zawartej na stronie nr. 8
Mainframe-class RAS Features Highly Available Center Plane System restoration after the replacement of a failed crossbar card no longer requires a planned system downtime The Express5800/1000 series server has separated and Crossbar Controller Mudularization Only the node that is linked directly to the failed crossbar modularized the crossbar controller which ordinarily would reside will be temporarily shutdown on the system center plane. By moving the crossbar controller off of the cent
Streszczenie treści zawartej na stronie nr. 9
Modularization, redundancy and domain segmentation of the system clock Minimizes downtime, and avoids multi-partition shutdown due to clock failure Through modularization and redundancy, system downtime, due to the oscillator, but also in the clock distribution mechanisms so that clock failures, have been minimized. The Express5800/1000 series system downtime can be minimized. server has taken it one step further. In many cases, when a system The 1320Xf system allows for the division of the
Streszczenie treści zawartej na stronie nr. 10
Mainframe-class RAS Features Enhanced error detection of the high-speed interconnect Intricate error handling through multi-bit error detection and resending of errored data Without Check Features Since higher speed interconnects are implemented to increase Bad data, resulting from a simple error Logic Circuits 1 bit Error system performance, there are higher probabilities that such as a single bit error, can not be blocked if a failure exists within the Data ECC chipset interferenc
Streszczenie treści zawartej na stronie nr. 11
Flexibility and Operability Pursuit of flexibility and operability in a system — Flexible resource virtualization using floating I/O for improved operability Investment Protection Smooth migration to future processors ® ® The Express5800/1000 series servers now support the Dual-Core � Intel Itanium Processor Family Roadmap ® ® 2002 2003 2004 2006 2007 Future Intel Itanium processors with two complete 64-bit cores on ® ® Dual-Core Intel Itanium 2 each processor. From the beginning of developmen
Streszczenie treści zawartej na stronie nr. 12
n NEC Express5800/1000 series Specifications Model 1080Rf 1160Xf 1320Xf ® ® Processor Dual Core Intel Itanium processor ® CPU Intel Processor Number 9120N 9140N 9150N 9120N 9140N 9150N 9120N 9140N 9150N Clock frequency 1.42GHz 1.60GHz 1.60GHz 1.42GHz 1.60GHz 1.60GHz 1.42GHz 1.60GHz 1.60GHz Maximum Number of CPU(core) 8 (16) 16 (32) 32 (64) L1 Cache/core 16KB (I) / 16KB (D) L2 Cache/core 1MB (I) / 256KB (D) On-chip cache L3 Cache/core 6MB 9MB 12MB 6MB 9MB 12MB 6MB 9MB 12MB L3 Cache/CPU 12MB 18MB
