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User’s Guide
User’s Guide
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EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product
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DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 0 Vdc to100 Vdc. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please con
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SLUU195 − June 2004 TPS40090 Multi-Phase Buck Converter and TPS2834 Drivers Steps-Down from 12-V to 1.5-V at 100 A Systems Power Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Schematic . . . . . . . . . . .
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SLUU195 − June 2004 2 Features Table 1. TPS40090EVM−002 Performance Summary PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input voltage range 10.5 12.0 14.0 V V Output voltage set point 1.477 1.508 1.540 Output current range V = 12 V 0 100 120 A IN I rising from 10 A to 100 A, (1) OUT Line regulation ±0.1% 10.5 V ≤ V ≤ 14 V IN Load regulation I rising from 10 A to 100 A ±0.3% OUT I rising from 10 A to 100 A −160 Load transient response voltage Load transient response voltage OUT mV mV PK PK chang
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SLUU195 − June 2004 TRANS_EN Figure 2. TPS40090EVM−002 Schematic Part 2 − Driver Circuit and Load Transient Generator 6 TPS40090 Multi-Phase Buck Converter and TPS2834 Drivers Steps-Down from 12-V to 1.5-V at 100 A
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SLUU195 − June 2004 + + + + + + + + 1.5V/100A Figure 3. TPS40090EVM−002 Schematic Part 3 − Power Stage 4 Component Selection 4.1 Frequency of Operation The clock oscillator frequency for the TPS40090 is programmed with a single resistor from RT (pin 16) to signal ground. Equation (1) from the datasheet allows selection of the R resistor in T kΩ for a given switching frequency in kHz. 3 1.024 (1) ( ) R R12 K 39.2 10 f 7 k T PH PH where • K is the coefficient that depends on the n
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SLUU195 − June 2004 4.2 Inductance Value The output inductor value for each phase can be calculated from the volt-second during off time, shown in equation (2). V V OUT OUT (2) L 1 f I V RIPPLE IN(max) where • I is usually chosen to be between 10% and 40% of maximum phase current I . RIPPLE PH(max) With I = 20% of I , there is a ripple current of 5 A, and the inductance value is found RIPPLE PH(max) to be 0.63 µH. Using SPM12550−R62M300 inductors from TDK, each had inductance of 0.6µH and
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SLUU195 − June 2004 0.6 0.5 N = 1 PH 0.4 0.3 N = 2 PH 0.2 N = 3 PH N = 4 PH 0.1 N = 6 PH 0 0 10 20 304050 60 7080 90 100 Duty Cycle − % Figure 4. Input Ripple Current RMS Value Overload Current The maximum input ripple RMS current can be estimated as shown in (4). (4) I I I 4, D 3.18 A OUT IN(nom) min It is also important to consider a minimum capacitance value which limits the voltage ripple to a specified value if all the current is supplied by the onboard capacitor. For a typical ri
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SLUU195 − June 2004 where • D is the duty cycle for a single phase • N is the number of active phases PH • K (N ) is the intermediate function for calculation PH In this case, N =4 and D =0.107 which yields k=0.573. PH min The actual output ripple is calculated in equation (7) V OUT 1.5 V (7) I K N ,D 0.573 3.41 A RIPPLE PH L f 0.6 H 420 kHz 1.0 N = 4 PH 0.8 0.6 N = 3 PH N = 1 PH 0.4 N = 2 PH 0.2 N = 6 PH 0 0 10 20 304050 60 7080 90 100 Duty Cycle − % Figure 5. Output Ripple Cur
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SLUU195 − June 2004 3. Transient consideration. An additional consideration in the selection of the output inductor and capacitance value can be derived from examining the transient voltage overshoot which can be initiated with a load step from full load to no load. By equating the inductive energy with the capacitive energy the equation (10) can be derived. 2 2 L I I 0.6H 2 EQ OH OL ( ) 100 A 2 (10) L I 4 C 1846F OUT 2 2 2 2 2 V (1.75 V) (1.5 V) V V O
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SLUU195 − June 2004 With the chosen inductor described in Inductance Value, (section 4.2, of this document) the following values are used. • R=19.6 kΩ • C=10 nF • R =100 kΩ NTC • R1=124 kΩ • R2=22.6 kΩ L DCR V V IN DCR L C DCR R V IN V OUT R1 C R R2 V C R NTC R THE UDG−03136 Figure 6. DCR Current Sensing Circuit with Copper Temperature Compensation 4.7 Overcurrent Limit Protection The overcurrent function monitors the voltage level separately on each current sense input and compares it to the vo
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SLUU195 − June 2004 4.8 Compensation Components The TPS40090 uses peak current mode control. Type II network is used here, which is implemented to provide one zero and two poles. The first pole is placed at the origin to improve DC regulation. The ESR zero of the power stage is: 1 (12) f 354 kHz ESRZ 2 R C C OUT The zero is placed near 3.96 kHz to produce a reasonable time constant. 1 (13) f Z 2 R11 C11 The second pole is placed at ESR zero (354 kHz). 1 f P1 (14) C11C12 2
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SLUU195 − June 2004 5 Test Setup The HPA072 has the following input/output connections: 12-V input J1 (VIN) and J2 (GND), 1.5-V output J9 (VOUT) and J10 (GND). A diagram showing the connection points is shown in Figure 5. A power supply capable of supplying 18 A should be connected to VIN and GND through a pair of 10 AWG wires. The 1.5-V load should be connected respectively to J9 and J10 through pairs of 0 AWG wires. Wire lengths should be minimized to reduce losses in the wires. A 5-inch fan w
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SLUU195 − June 2004 6 Test Results and Performance Data 6.1 Efficiency and Power Loss Figure 8 shows the efficiency as the load varies from 10 A to over 100 A. The efficiency at full load is about 84.3%. Figure 7 shows the total loss versus the load current, which is approximately 28.3W at 100 A. OVERALL EFFICIENCY TOTAL POWER LOSS vs vs OUTPUT CURRENT OUTPUT CURRENT 40 90 V = 12 V IN V = 12 V IN f = 420 kHz SW f = 420 kHz SW 35 85 30 25 80 20 75 15 10 70 5 0 65 0 20 40 60 80 100 120 0 20 40 60
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SLUU195 − June 2004 6.2 Closed-Loop Performance The TPS40090 uses peak current-mode control. Figure 10 shows the bode plots at 100 A of load current, where no droop function is implemented. The crossover frequency is at 89 kHz with phase margin of 40°. GAIN AND PHASE vs OSCILLATOR FREQUENCY 80 180 135 60 PHASE 90 40 45 20 0 −45 0 −90 GAIN −20 V = 12 V IN −135 V = 1.5 V OUT I = 10 A OUT −40 −180 100 1 k 10 k 100 k 1 M f − Oscillator Frequency − kHz OSC Figure 10. Bode Plot 6.3 Output Ripple and N
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SLUU195 − June 2004 6.4 Transient Response The on-board load transient circuit enables to check the step load transient response on the same board. Simply by putting a jumper to connect Pin1 and 2 of J3, a 90-A step load is created by three 50-mΩ resistors placed on the board. The slew rates of the transient are 200 A/µs for the load step-down and 160 A/µs for the load step-up. The transient response is shown in Figure 6 as the load is stepped from 10 to 100 A. The output deviation is approximat
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SLUU195 − June 2004 6.5 Start up with Pre-Biased Output In synchronous buck converter, the bottom FET discharges the pre-biased output during start-up. To avoid this, a comparator U9 and surround components are used to pull the SYNC pin of the drivers low, which keeps the bottom FET off during startup. So the output can rise smoothly. After the SS pin comes up, SYNC is pulled up high and enable the bottom FET’s driving signal. The converter goes back to normal synchronization mode. This function
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SLUU195 − June 2004 7 Layout Considerations The PCB layout plays a critical role in the performance in a high frequency switching power supply design. Following the suggestions listed below will help to improve the performance and expedite the design. • To take full advantage of the ripple cancellation factor from interleaving, place the input capacitors before the junction where the input voltage is distributed to each phase. Place the output capacitors after the junction where all the inductor
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SLUU195 − June 2004 8 EVM Assembly Drawing and PCB Layout Figure 15. Top Side Component Assembly Figure 16. Bottom Assembly 20 TPS40090 Multi-Phase Buck Converter and TPS2834 Drivers Steps-Down from 12-V to 1.5-V at 100 A
