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®
Intel NetStructure MPCBL0010
Single Board Computer
Technical Product Specification
October 2006
Order Number: 304120
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® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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—MPCBL0010 Contents 1.0 Introduction ............................................................................................................ 12 1.1 Document Organization...................................................................................... 12 1.2 Glossary .......................................................................................................... 13 2.0 Feature Overview ............................................................................................
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MPCBL0010— 3.8.2.1 Synchronizing BIOS Image and Settings from FWH0 (Main) to FWH1 (Backup)33 3.8.2.2 Copying BIOS.bin from the SBC ..................................................34 3.8.2.3 Saving BIOS.bin to the SBC........................................................34 3.8.2.4 flashlnx Command Line Options.................................................35 3.8.3 IPMC Firmware Updates...........................................................................35 3.8.3.1 IPMC Firmware Upgrad
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—MPCBL0010 7.0 BIOS Setup.............................................................................................................. 62 7.1 Introduction ..................................................................................................... 62 7.2 Main Menu ....................................................................................................... 62 7.3 Advanced Menu................................................................................................. 63
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MPCBL0010— 10.8.2 Board Device Channel Port Selection Identifiers ........................................131 10.8.2.1 SetBoardDeviceChannelPortSelection .........................................132 10.8.2.2 GetBoardDeviceChannelPortSelection.........................................133 10.8.2.3 GetBoardDevicePossibleSelection...............................................133 10.8.3 Set Control State..................................................................................134 10.8.4 Get C
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—MPCBL0010 11.8.2.3 Start an SOL Session............................................................... 158 11.8.2.4 Checking SOL Configuration ..................................................... 158 11.8.2.5 Ending an SOL Session ............................................................ 159 11.9 Operating Systems for SOL Client (ipmitool) ....................................................... 160 12.0 Telecom Clock ..........................................................................
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MPCBL0010— 17.3 Sales Assistance..............................................................................................183 17.4 Product Code Summary ....................................................................................183 18.0 Certifications .........................................................................................................184 19.0 Agency Information—Class B .................................................................................185 19.1 North
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—MPCBL0010 Tables 1 Supported Memory Configurations.............................................................................. 18 2 Jumper Definitions ................................................................................................... 26 3 Suggested Method of BIOS Image Synchronization prior to BIOS Upgrade ....................... 33 4 Flashlnx Utility Command Line Options........................................................................ 35 5 Environmental Specifications
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MPCBL0010— 54 OS Load Timeout Timer Sub-Menu..............................................................................85 55 Security Menu..........................................................................................................85 56 Chipset Menu...........................................................................................................86 57 Northbridge Chipset Configuration ..............................................................................86 58 Spre
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—MPCBL0010 109 Hardware Sensors.................................................................................................. 117 110 OEM Sensor Types ................................................................................................. 120 111 OEM Event/Reading Type ........................................................................................ 121 112 SEL Events Supported ............................................................................................ 121 1
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MPCBL0010— Revision History Date Revision Description Updated to include the following: -- new Chapter 11, “Serial over LAN” -- CMOS_CLR jumper change -- new sensor threshold data -- change to sensor name, Temp CPLD Area September 2006 002 -- new section 3.8.2.1 for other flashInx command options -- new information about using ipmitool in section 3.8.3 -- corrected duplicate section names in 4.3.2 and 4.3.3 -- new note in section 6.7 to clarify additional boot options -- new sysfs interface subs
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MPCBL0010—Introduction 1.0 Introduction 1.1 Document Organization ® This document provides technical specifications related to the Intel NetStructure MPCBL0010 Single Board Computer (SBC). The MPCBL0010 SBC is designed following the standards of the Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high availability, switched network computing. This document is intended for support during system product development and while sustaining a product. It specifies
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Introduction—MPCBL0010 Chapter 13.0, “Maintenance” includes supervision and diagnostics information. Chapter 14.0, “Thermals” describes pressure drop curves versus the flow rate in accordance with PICMG 3.0 Specification.. Chapter 15.0, “Component Technology” lists the major components used on the MPCBL0010. Chapter 16.0, “Warranty Information” provides warranty information for Intel ® NetStructure products. Chapter 17.0, “Customer Support” provides information on how to contact customer sup
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MPCBL0010—Introduction ® IBA Intel Boot Agent. The Intel Boot Agent is a software product that allows your networked client computer to boot using a program code image supplied by a remote server. IDE Integrated Device Electronics. Common, low-cost disk interface. IPMB Intelligent Platform Management Bus. Physical two-wire medium to carry IPMI. IPMC Intelligent Platform Management Controller. ASIC on baseboard responsible for low-level system management. IPMI Intelligent Platform Management
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Feature Overview—MPCBL0010 SBC 2.0 Feature Overview 2.1 Application The Advanced Telecommunications Compute Architecture (AdvancedTCA*) standards define open architecture modular computing components for a carrier-grade, communications network infrastructure. The goals of the standards are to enable blade-based modular platforms to be: •cost effective • high-density • high-availability • scalable These systems use a fabric I/O network for connecting multiple, independent processor boards, I/
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Backplane Front Panel MPCBL0010 SBC—Feature Overview Figure 1. MPCBL0010 Block Diagram Firmware Hub Firmware Hub Firmware Hub Firmware Hub VRM VRM (FWH0) (FWH1) (FWH0) (FWH1) LEDs LEDs FPGA 33 MHz LPC Tw Two o Tw Two o (4MB/s) 240-p 240-piin D n DIIM MM M IPMC On-board On-board 240-p 240-piin D n DIIM MM M Soc Sock kets ets Power Soc Sock kets ets Power RJ-45 Supplies RJ-45 Supplies DDR2 400 DDR2 400 10/100 DDR2 400 DDR2 400 AGTL LV Intel® Xeon™ and Hot 10/100 and Hot LV Int
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Feature Overview—MPCBL0010 SBC ® •Intel 6700PXH 64-bit PCI Hub A brief overview is provided here and detailed component information can be found in each device’s respective documentation. 2.2.2.1 Memory Controller Hub ® The architecture of the Intel E7520 MCH provides the performance and feature set required for performance servers, with configuration options facilitating optimization of the platform for workloads characteristic of communication, presentation, storage, performance computatio
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MPCBL0010 SBC—Feature Overview Note: Two 25-degree 240-pin DIMMs theoretically support memory configurations up to 8 GBytes of PC2-3200 registered DDR2-400 SDRAM, but only memory configurations of 2 GBytes and 4 GBytes have been validated. Table 1. Supported Memory Configurations Total Memory J10 J12 2 GBytes 1 GByte DDR2-400 DIMM 1 GByte DDR2-400 DIMM 4 GBytes 2 GBytes DDR2-400 DIMM 2 GBytes DDR2-400 DIMM ® Note: See the Intel NetStructure MPCBL0010 High-Performance Single Board Computer Com
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Feature Overview—MPCBL0010 SBC The hardware may support an assignable decode space; however, the BIOS will set this space prior to handing it over to the OS. It is not expected that the OS will move the location of these timers once the space is set by the BIOS. In the 6300ESB ICH, one timer block is implemented. The timer block has one counter and three timers (comparators). Various capabilities registers indicate the number of timers and the capabilities of each. 2.2.4.3.1 Timer Accuracy T
