Streszczenie treści zawartej na stronie nr. 1
48-V to 3.3-V Forward Converter with
Active Clamp Reset Using the
UCC2891 Active Clamp Current Mode
PWM Controller
User's Guide
December 2006 Power Supply MAN
SLUU178A
Streszczenie treści zawartej na stronie nr. 2
48-V to 3.3-V Forward Converter with Active Clamp Reset Using the UCC2891 Active Clamp Current Mode PWM Controller User's Guide Literature Number: SLUU178A November 2003–Revised December 2006
Streszczenie treści zawartej na stronie nr. 3
User's Guide SLUU178A–November 2003–Revised December 2006 Using the UCC2891 Active Clamp Current Mode PWM Controller 1 Introduction The UCC2891EVM evaluation module (EVM) is a forward converter providing a 3.3-V regulated output at 30 A of load current, operating from a 48-V input. The EVM operates over the full 36 V to 72 V telecom input range, and is able to fully regulate down to zero load current. The module uses the UCC2891 current mode active clamp PWM controller for effectively demonstrat
Streszczenie treści zawartej na stronie nr. 4
www.ti.com Description 2.1 Applications The UCC2891 is suited for use in isolated telecom 48-V input systems requiring high-efficiency and high-power density for very low-output voltage, high-current converter applications, including: • Server Systems • Datacom • Telecom • DSP's, ASIC's, FPGA's 2.2 Features The UCC2891EVM features include: • ZVS transformer reset using active clamp technique in forward converter • All surface mount components, double sided half brick (2.2 × 2.28 × 0.5) inches •
Streszczenie treści zawartej na stronie nr. 5
www.ti.com UCC2891EVM Electrical Performance Specifications 3 UCC2891EVM Electrical Performance Specifications The UCC2891EVM electrical performance specifications are listed in Table 1. Table 1. UCC2891EVM Performance Summary PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Characteristics Input voltage range 36 48 72 V No load intput current V = 36 V, I = 0 A 75 100 mA IN OUT Maximum input current V = 36 V, I = 30 A 3.00 3.25 A IN OUT Input voltage ripple V = 72 V, I = 30 A 1.50 1.75 V IN OUT
Streszczenie treści zawartej na stronie nr. 6
www.ti.com Schematic Figure 1. UCC2891EVM Schematic 6 Using the UCC2891 Active Clamp Current Mode PWM Controller SLUU178A–November 2003–Revised December 2006 Submit Documentation Feedback + + + +
Streszczenie treści zawartej na stronie nr. 7
- - + - www.ti.com EVM Test Setup High efficiency is achieved using self-driven synchronous rectification on the secondary side. Q3 and Q4 are placed in parallel and make up the forward synchronous rectifier (SR), while the reverse SR is made up of the parallel combination of Q5, Q7 and Q8. If the duty cycle were limited to 50% then the reverse SR could be reduced to only two parallel MOSFETs, but since these devices are operating near 60% duty cycle during the freewheel mode, they carry a highe
Streszczenie treści zawartej na stronie nr. 8
www.ti.com EVM Test Setup 5.1 Output Load (LOAD1) For the output load to VOUT, a programmable electronic load set to constant current mode and capable of sinking between 0A and 30A , is used. Using a dc voltmeter, V2, it is also advised to make all output DC DC voltage measurements directly at J9 and J10 pins. Unless the load has remote sense capability, measuring VOUT at LOAD1 results in some voltage measurement error, especially at higher load current, due to finite voltage drops across the wi
Streszczenie treści zawartej na stronie nr. 9
www.ti.com Power Up/Down Test Procedures 6 Power Up/Down Test Procedures The following test procedure is recommended primarily for power up and shutting down the EVM. Whenever the EVM is running above an output load of 15 A , the fan should be turned on. Also, never DC walk away from a powered EVM for extended periods of time. 1. Working at an ESD workstation, make sure that any wrist straps, bootstraps or mats are connected referencing the user to earth ground before power is applied to the EVM
Streszczenie treści zawartej na stronie nr. 10
www.ti.com Power Up/Down Test Procedures 7 Power Up/Down Test Procedures OVERALLEFFICIENCY vs OUTPUTCURRENT 93 V =48V IN 91 89 V =72V IN V =36V IN 87 85 83 81 V =3.3V OUT f = 300kHz S 79 2 6 10 14 18 22 26 I -OutputCurrent-A OUT Figure 3. POWERLOSS GAINANDPHASE vs vs OUTPUTCURRENT FREQUENCY 12 60 180 V =3.3V OUT Phase f = 300kHz S 40 120 10 20 60 8 Gain 0 0 6 -20 -60 V =72V IN V =36V IN I = 10A -40 OUT -120 V =48V IN g =-8dB 4 M F =50° M -60 -180 10 100 1k 10k 100k V =36V IN 2 f-Frequency-Hz 2 6
Streszczenie treści zawartej na stronie nr. 11
www.ti.com Power Up/Down Test Procedures Input Ripple Voltage GAINANDPHASE vs FREQUENCY 60 180 V = 36 V IN I = 30 A OUT Phase 40 120 500 mV/div 1 V peak-to-peak 20 60 0 0 Gain -20 -60 V =48V IN I = 10A -40 OUT -120 g =-10dB M F =50° M -60 -180 10 100 1k 10k 100k t − Time − 2.5 μs/div f-Frequency-Hz Figure 8. Figure 6. Output Ripple Voltage GAINANDPHASE vs FREQUENCY V = 72 V IN 60 180 I = 30 A OUT Phase 40 120 50 mV/div 36 mV peak-to-peak 20 60 0 0 Gain -20 -60 V =72V IN I = 10A -40 OUT -120 g =-
Streszczenie treści zawartej na stronie nr. 12
www.ti.com Power Up/Down Test Procedures Output Ripple Voltage SR Gate Drive V = 36 V V = 36 V IN IN I = 30 A OUT 6.3 V, QF Gate (J5) (5 V/div) 50 mV/div 23 mV peak-to-peak 8.4 V, QR Gate (J6) (5 V/div) t − Time − 1 μs/div t − Time − 2.5 μs/div Figure 12. Figure 10. SR Gate Drive Transformer Primary V = 72 V V = 48 V IN IN I = 10 A OUT 12.3 V, QF Gate (J5) V PRI (5 V/div) (40 V/div) I PRI (0.5 A/div) 5.4 V, QR Gate (J6) (5 V/div) t − Time − 1 μs/div t − Time − 2.5 μs/div Figure 13. Figure 11. 12
Streszczenie treści zawartej na stronie nr. 13
www.ti.com EVM Assembly Drawing and Layout 8 EVM Assembly Drawing and Layout Figure 14 through Figure 20 show the top-side and bottom-side component placement for the EVM, as well as device pin numbers where necessary. A four layer PCB was designed using the top and bottom layers for signal traces and component placement along with an internal ground plane. The PCB dimensions are 3.6" x 2.7" with a design goal of fitting all components within the industry standard half-brick format, as outlined
Streszczenie treści zawartej na stronie nr. 14
www.ti.com EVM Assembly Drawing and Layout Figure 15. Top Side Silk Screen Figure 16. Top Signal Trace Layer 14 Using the UCC2891 Active Clamp Current Mode PWM Controller SLUU178A–November 2003–Revised December 2006 Submit Documentation Feedback
Streszczenie treści zawartej na stronie nr. 15
www.ti.com EVM Assembly Drawing and Layout Figure 17. Internal Split Ground Plane Figure 18. Internal Signal Trace Layer SLUU178A–November 2003–Revised December 2006 Using the UCC2891 Active Clamp Current Mode PWM Controller 15 Submit Documentation Feedback
Streszczenie treści zawartej na stronie nr. 16
www.ti.com EVM Assembly Drawing and Layout Figure 19. Bottom Signal Trace Layer Figure 20. Bottom Side Component Assembly 16 Using the UCC2891 Active Clamp Current Mode PWM Controller SLUU178A–November 2003–Revised December 2006 Submit Documentation Feedback
Streszczenie treści zawartej na stronie nr. 17
www.ti.com List of Materials 9 List of Materials The following table lists the UCC2891EVM components corresponding to the schematic shown in Figure 1. Table 2. List of Materials QT REF DESCRIPTION MFR PART NUMBER Y C1, C2, C4 3 Capacitor, ceramic, 2.2 μF, 100 V, X7R, 20%, 1812 TDK C4532X7R2A225M C3, C14, C17 3 Capacitor, ceramic, 0.1 μF, 50 V, X7R, 20%, 805 Vishay VJ0805Y104MXAA C5 1 Capacitor, ceramic, 100 pF, 50 V, NPO, 10%, 805 Vishay VJ0805A101KXAA C6, C7 2 Capacitor, ceramic, 0.22 μF, 50 V,
Streszczenie treści zawartej na stronie nr. 18
www.ti.com References Table 2. List of Materials (continued) QT REF DESCRIPTION MFR PART NUMBER Y R1 1 Resistor, chip, 8.45 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-8451-F R2 1 Resistor, chip, 57.6 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-5762-F R3 1 Resistor, chip, 76.8 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-7682-F R4, R10, R15, R16, 7 Resistor, chip, 2.21 Ω, 1/10 W, 1%, 805 Vishay CRCW0805-2R21-F R20, R23, R24 R5 1 Resistor, chip, 158 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-1583-F R6 1 Resistor, chip, 1.82 kΩ,
Streszczenie treści zawartej na stronie nr. 19
EVMIMPORTANTNOTICE Texas Instruments (TI)provides the enclosed product(s)underthe following conditions: This evaluation kitbeing sold by TI is intended foruse forENGINEERINGDEVELOPMENTOR EVALUATIONPURPOSESONLYandisnotconsideredbyTItobefitforcommercialuse.Assuch, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically foundintheendproductincorporatingthegoods.Asaproto
Streszczenie treści zawartej na stronie nr. 20
DYNAMICWARNINGSANDRESTRICTIONS Itis importantto operate this EVMwithin the inputvoltage range of0 Vdc to 72 Vdc. Exceedingthespecifiedinputrangemaycauseunexpectedoperationand/orirreversibledamage to the EVM. If there are questions concerning the input range, please contact a TI field representative priorto connecting the inputpower. Applying loads outside of the specified output range may result in unintended operation and/or possiblepermanentdamagetotheEVM.PleaseconsulttheEVMUser’sGuidepriortoc
