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E2E1027-27-Y4
This version: Jan. 1998
¡ Semiconductor MSM66201/66P201/66207/66P207
¡ Semiconductor Previous version: Nov. 1996
MSM66201/66P201/66207/
66P207
OLMS-66K Series 16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66201/66207 is a high performance microcontroller that employs OKI original nX-8/
200 CPU core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit
timers, 10-bit A/D converter, serial I/O port, and pulse width modulator (PWM). The
MSM66P201/66P207 is
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¡ Semiconductor MSM66201/66P201/66207/66P207 • Package 64-pin plastic shrink DIP (SDIP64-P-750-1.78) : (MSM66201-´´´SS) (MSM66P201-´´´SS) (MSM66207-´´´SS) (MSM66P207-´´´SS) 64-pin plastic QFP (QFP64-P-1414-0.80-BK) : (MSM66201-´´´GSBK)(MSM66207´´´GS- BK) 68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27) : (MSM66201-´´´JS) (MSM66P201-´´´JS) (MSM66207-´´´JS) (MSM66P207-´´´JS) 64-pin ceramic piggyback (ADIP64-C-750-1.78) : (MSM66G207VS) (´´´ indicates the code number.) * The piggyback type is used only
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¡ Semiconductor MSM66201/66P201/66207/66P207 BLOCK DIAGRAM P5 P4 P3 P2 P1 P0 HLDA/P2.5 HOLD/P2.4 FLT RES OSC1 OSC0 GND V DD 3/30 P4.0/TM0CK P4.1/TM1CK TIMER SSP LRB P3.4/TM0IO 0–3 P3.7/TM3IO P3.1/RXD EA P3.0/TXD SERIAL B P2.7/RXC PORT READY U P2.6/TXC S ALE *2 P4.4/TRNS0 PSW RAM P PSEN TRANSI- 1024 ´ 8 bits O TION D. RD P4.7/TRNS3 R T WR V REF P5.0/AI 0 MEMORY C AD0/P0.0 A/D ALU O CONV. CONT. P5.7/AI 7 N AD7/P0.7 AGND T . PC *1 RAP P4.2/PWM0 A8 /P1.0 PWM P4.3/PWM1 0,1 ROM 32K ´ 8 bits A15/P
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¡ Semiconductor MSM66201/66P201/66207/66P207 PIN CONFIGURATION (TOP VIEW) AD0/P0.0 1 64 V DD AD1/P0.1 2 63 V REF AD2/P0.2 3 62 AGND AD3/P0.3 4 61 P5.7/AI7 AD4/P0.4 5 60 P5.6/AI6 AD5/P0.5 6 59 P5.5/AI5 AD6/P0.6 7 58 P5.4/AI4 AD7/P0.7 8 57 P5.3/AI3 A8/P1.0 9 56 P5.2/AI2 A9/P1.1 10 55 P5.1/AI1 A10/P1.2 11 54 P5.0/AI0 A11/P1.3 12 53 P4.7/TRNS3 A12/P1.4 13 52 P4.6/TRNS2 A13/P1.5 14 51 P4.5/TRNS1 A14/P1.6 15 50 P4.4/TRNS0 A15/P1.7 16 49 P4.3/PWM1 P2.0 17 48 P4.2/PWM0 P2.1 18 47 P4.1/TM1CK P2.2 19 46 P
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¡ Semiconductor MSM66201/66P201/66207/66P207 PIN CONFIGURATION (TOP VIEW) (Continued) A8/P1.0 1 48 P5.2/AI2 A9/P1.1 2 47 P5.1/AI1 A10/P1.2 3 46 P5.0/AI0 A11/P1.3 4 45 P4.7/TRNS3 A12/P1.4 5 44 P4.6/TRNS2 A13/P1.5 6 43 P4.5/TRNS1 A14/P1.6 7 42 P4.4/TRNS0 A15/P1.7 8 41 P4.3/PWM1 P2.0 9 40 P4.2/PWM0 P2.1 10 39 P4.1/TM1CK P2.2 11 38 P4.0/TM0CK CLKOUT/P2.3 12 37 P3.7/TM3IO RESOUT 13 36 P3.6/TM2IO ALE 14 35 P3.5/TM1IO PSEN 15 34 P3.4/TM0IO RD 16 33 P3.3/INT1 64-Pin Plastic QFP 5/30 WR 17 64 P0.7/AD7
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¡ Semiconductor MSM66201/66P201/66207/66P207 PIN CONFIGURATION (TOP VIEW) (Continued) AI3/P5.3 P3.2/INT0 61 43 AI4/P5.4 P3.1/RXD 62 42 AI5/P5.5 P3.0/TXD 63 41 AI6/P5.6 P2.7/RXC 64 40 AI7/P5.7 P2.6/TXC 65 39 AGND P2.5/HLDA 66 38 V P2.4/HOLD 67 37 REF V NMI 68 36 DD V GND 1 35 DD AD0/P0.0 2 34 GND AD1/P0.1 3 33 OSC1 AD2/P0.2 4 32 OSC0 AD3/P0.3 5 31 RES AD4/P0.4 6 30 FLT AD5/P0.5 7 29 EA AD6/P0.6 READY 8 28 AD7/P0.7 WR 9 27 NC : No-connection pin 68-Pin Plastic QFJ (PLCC) 6/30 A8/P1.0 P5.2/AI2 1
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¡ Semiconductor MSM66201/66P201/66207/66P207 PIN DESCRIPTION Symbol Type Description P0.0–P0.7/ I/O P0: 8-bit input-output port. Each bit can be assigned to input or output. AD0–AD7 AD: Outputs the lower 8 bits of program counter during external program memory fetch, and receives the addressed instruction under the control of PSEN. This pin also outputs the address and outputs or inputs data during an external data memory access instruction, under the control of ALE, RD, and WR.
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¡ Semiconductor MSM66201/66P201/66207/66P207 PIN DESCRIPTION (Continued) Symbol Type Description RESOUT Outputs "H" level in the case of internal reset. O Reset to"L" level by program. ALE Address Latch Enable: O The timing pulse to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory. O The strobe pulse to fetch to external program PSEN Program Strobe Enable: memory. RD O Output strobe activated during a bus read cycle. Used to enable data onto t
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¡ Semiconductor MSM66201/66P201/66207/66P207 REGISTERS Accumulator 15 0 ACC Control Register (CR) 15 0 PSW Bit 15 : Carry flag (CY) Bit 14 : Zero flag (ZF) Bit 13 : Half carry flag (HC) Bit 12 : Data descriptor (DD) Bit 8 : Master interrupt priority flag (MIP) Bit 9,5,4: User flag (MIP) Bit 2-0 : System control base 2-0 (SCB2-0) 15 0 PC LRB SSP Pointing Register (PR) 15 0 X1 Index Register 1 X2 Index Register 2 DP Data Pointer User Stack Pointer USP Local Register 7070 ER0 R1
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¡ Semiconductor MSM66201/66P201/66207/66P207 SFR Address 8/16-bit Name Symbol R/W Reset Operation (HEX) 0000 FFH SSP System stack printer 0001 (ASSP) FFH 0002 LRB undefined Local register base 0003 (ALRB) R/W 8/16 PSWL 0004I
C8H (APSW) Program status word 0005I
PSWH 0CH 0006 00H Accumulator ACC 0007 00H 0010I
F8H Standby control register SBYCON 00H/WDT 0011 Watchdog timer WDT W is stopped 8 0012I
Peripheral control register PRPHF FDH R/W 0013 Stop code acceptor STPACP W "0" 0018 00H Interrup
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¡ Semiconductor MSM66201/66P201/66207/66P207 SFR (Continued) Addres Abbreviated 8/16-bit Name R/W Reset Name Operation (HEX) 0038 00H Timer 2 counter TM2 0039 00H 003A 00H Timer 2 register TMR2 003B 00H 16 003C 00H Timer 3 counter TM3 003D 00H 003E 00H Timer 3 register TMR3 003F 00H 0040 Timer 0 control register 00H TCON0 0041 00H Timer 1 control register TCON1 R/W 0042 Timer 2 control register TCON2 00H 0043 Timer 3 control register TCON3 00H 0046I
Transition detector register undefined TRNSIT
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¡ Semiconductor MSM66201/66P201/66207/66P207 SFR (Continued) Address Abbreviated 8/16-bit Name R/W Reset Name operation (HEX) 0062I
A/D conversion result register 1 ADCR1 0063 0064I
A/D conversion result register 2 ADCR2 0065 0066I
A/D conversion result register 3 ADCR3 0067 R undefined 0068I
A/D conversion result register 4 ADCR4 0069 006AI
A/D conversion result register 5 ADCR5 006B 006CI
A/D conversion result register 6 ADCR6 8/16 006D 006EI
A/D conversion result register 7 ADCR7 006F
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¡ Semiconductor MSM66201/66P201/66207/66P207 ADDRESSING MODES The MSM66201/66207 provides independent 64K-byte data and 64K-byte program space with various types of addressing modes. These modes are shown below, for both RAM (for data space) and ROM (for program space). 1. RAM Addressing Modes (for data space) 1.1 Register Direct Addressing Example ROR DP DP 1.2 Displacement Addressing a) Zero Page Example 0000H L A, 18H SFR 0018H b) Direct Page Example xx00H ST A, off 10H RAM xx10H 1.3 Pointing
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¡ Semiconductor MSM66201/66P201/66207/66P207 c) Index Register (X1, X2) Indirect Example INC 300H [X1] RAM X1 0 to 65535 1.4 Immediate Addressing Example MOV SSP, #27FH 2. ROM Addressing Modes (for program space) 2.1 Direct Addressing Example 200H LC A, ROM 0200H 2.2 Simple Indirect Addressing a) Local Register Indirect Example LC A,[ER0] ROM ER0 b) Pointing Register Indirect 1) Data Pointer (DP) Indirect Example LC A, [DP] ROM DP 2) User Stack Pointer (USP) Indirect Example LC A,[USP] ROM
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¡ Semiconductor MSM66201/66P201/66207/66P207 3) Index Register (X1, X2) Indirect Example LC A, [X1] ROM X1 c) System Stack Pointer (SSP) Indirect Example LC A,[SSP] ROM SSP d) Local Register Base (LRB) Indirect Example LC A,[LRB] ROM LRB e) RAM Indirect Example J A, [0C0H] RAM ROM 0C0H 2.3 Double Indirect Addressing a) Data Pointer (DP) Double Indirect Example J [[DP]] RAM ROM DP b) User Stack Pointer (USP) Double Indirect Example LC A, [–2 [USP]] RAM ROM USP –128 to +127 15/30
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¡ Semiconductor MSM66201/66P201/66207/66P207 c) Index Register (X1, X2) Double Indirect Example LC A, [10000H [x1]] RAM ROM X1 0 to 65535 2.4 Indirect Addressing with 16-bit Offset a) Pointing Register Indirect 1) Data Pointer (DP) Indirect Example LC A, [100H [DP]] ROM DP 0 to 65535 2) User Stack Pointer (USP) Indirect Example LC A, [100H [USP]] ROM USP 0 to 65535 3) Index Register (X1, X2) Indirect Example LC A, [100H [X1]] ROM X1 0 to 65535 b) RAM Indirect Example LC A, [2000H [80H]
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¡ Semiconductor MSM66201/66P201/66207/66P207 MEMORY MAPS Program Memory Space 0000H 0000H Vector Table Area (40 bytes) 0027H Internal 0028H VCAL ROM Area Table Area (16 bytes) 0037H 0038H 7FFFH * External Memory FFFFH 7FFFH * * MSM66201 : 3FFFH Data Memory Space 0000H 0000H SFR Area Special 007FH Function 0080H Zero PR Area Registors 00BFH Page 00C0H 00FFH PORT, A/DC, 0100H TIMER, PWM, etc.... 007FH Internal 80 0080H PR0 (Low Order) RAM X1 Area PR1 (High Order) 82 PR2 X2 047FH * PR3 84 PR4 DP PR
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¡ Semiconductor MSM66201/66P201/66207/66P207 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Parameter Symbol Condition Rating Unit Supply Voltage V –0.3 to 7.0 DD Input Voltage V –0.3 to V +0.3 I DD Output Voltage V –0.3 to V +0.3 V O GND=AGND=0V DD Analog Ref. Voltage V –0.3 to V +0.3 REF DD Analog Input Voltage V –0.3 to V AI REF 64-pin shrink DIP 930 Ta=85°C Power Dissipation P 64-pin QFP 565 mW D per Package 68-pin QFJ 1120 Storage Temperature T –55 to +150 °C STG — RECOMMENDED OPERATING CONDITIONS Para
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¡ Semiconductor MSM66201/66P201/66207/66P207 ELECTRICAL CHARACTERISTICS DC Characteristics (V = 5V ± 10%, Ta = –40 to +85°C) DD Parameter Symbol Condition Min. Typ. Max. Unit "H" Input Voltage 1, 3, 6 2.4 — V +0.3 DD "H" Input Voltage 5, 7 4.0 — V +0.3 DD V — IH "H" Input Voltage 8 4.2 — V +0.3 DD "H" Input Voltage 2 3.6 — V +0.3 DD "L" Input Voltage 1, 2, 3, 6 –0.3 — 0.8 "L" Input Voltage 5, 7 V — –0.3 — 0.8 V IL "L" Input Voltage 8 –0.3 — 0.4 "H" Output Voltage 1, 4 4.2 — — I
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¡ Semiconductor MSM66201/66P201/66207/66P207 AC Characteristics • External program memory control (V =5V±10%, Ta=–40 to +85°C) DD Parameter Symbol Condition Min. Max. Unit Clock (OSC) Pulse t — 50 — fW ALE Pulse Width t 3t — AW fW–20 PSEN Pulse Width t 4t — PW fW–20 PSEN Pulse Delay Time t t t PAD fW–20 fW+20 Low Address Setup time t 2t 2t AAS fW–35 fW+20 ns Low Address Hold Time t C = 50pF t t AAH L fW–20 fW+40 High Address Delay Time t t t AAD fW–20 fW+40 High Address Hold Time t t t APH fW–20
