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The DP8400 Family of Memory Interface Circuits AN-302
National Semiconductor
The DP8400 Family of
Application Note 302
Charles Carinalli
Memory Interface Circuits
Mike Evans
February 1986
INTRODUCTION The DP8409A multi-mode dynamic RAM controller/driver
was the first controller to resolve all of these problems. This
The rapid development in dynamic random access memory
Schottky bipolar device provides the flexibility of external
(DRAM) chip storage capability, coupled with significant
access con
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Indicates that there is a 3 kX pull-up resistor on these outputs when they are disabled. TL/F/5012±1 FIGURE 1. DP8409A Block Diagram TABLE II. DP8409A Mode Select Options (RFSH) Mode M1 M0 Mode of Operation Conditions M2 0 0 0 0 Externally Controlled Refresh RF I/O e EOC 1 0 0 1 Auto RefreshÐForced RF I/O e Refresh Request (RFRQ) e 2 0 1 0 Internal Auto Burst Refresh RF I/O EOC e 3a 0 1 1 All RAS Auto Write RF I/O EOC 3b 0 1 1 Externally Controlled All RAS Access All RAS Active 4 1 0 0 Externall
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Drams may be 16k, 64k or 256k For 4 banks, can drive 16 data a bits 6 check bits for ECC. For 2 banks, can drive 32 data a bits 7 check bits for ECC. For 1 bank, can drive 64 data a bits 8 check bits for ECC. *These outputs may need damping resistors to prevent overshoot, undershoot at memories. TL/F/5012±2 FIGURE 2. Typical Application of DP8409A Using External Control and Refresh in Modes 0 and 4 TL/F/5012±3 FIGURE 3. This figure demonstrates the automatic accessing capability of the DP8409A.
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Refreshing curred, via the refresh request output (RF I/O pin). The sys- tem acknowledges the request for a forced refresh by set- The DP8409A also provdes hidden refresh capability while ting M2 (refresh) low on the DP8409A and preventing fur- in one of the automatic access modes (Figure 4). In this ther access to the DP8409A. The DP8409A then uses mode, it will automatically perform a refresh without the sys- RGCK to generate an automatic forced refresh. The refresh tem being interrupted. To d
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Two new devices are now available for this application. The with this high speed, chip power dissipation is still main- DP84240 is pin and function compatible with the tained at a reasonable level as demonstrated by the graphs DM74S240. The DP84244 is likewise compatible with the shown in Figures 7a, 7b of power versus frequency. DM74S244. However, this is where the similarity between The DP84240 and the DP84244 are fabricated on a high the devices ends. Both the DP84240 and the DP84244 performa
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through these driversÐa delay not shown by the data sheet specifications. Additionally, the problem becomes increas- ingly severe as multiple driver inputs are used in parallel for bus expansion applications. Both the DP84240 and the DP84244 are designed to signifi- cantly reduce both static and dynamic input capacitance. When these devices are driven with standard logic circuits, no appreciable overhead delay need be added to the basic device delay specifications due to input pulse distortion.
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TABLE IV. Check Bit Overhead for Multiple Bit Error to 80-bit data words. It is a 16-bit chip that is easily expand- Detection and Single Bit Error Correction able with the simple addition of more DP8400s for each 16- bit word increment. Number of Bits Number of Percentage Figures 9a, 9b and9c demonstrate its basic operation in the in Memory Check Bits of Excess write and read memory access cycles.Figure 9a shows the Data Word Required Memory normal write cycle, where system data is used by the
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TL/F/5012±11 FIGURE 9a. Normal Write Mode with DP8400 TL/F/5012±12 FIGURE 9b. Normal Read Mode Using the Error Monitoring Method with the DP8400 TL/F/5012±13 FIGURE 9c. Normal Read Mode Using the Always Correct Method with the DP8400 *C2, C3 generate odd parity TL/F/5012±14 FIGURE 10. DP8400 Matrix 8
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A key advantage of the DP8400 is that it has three error Double Bit Error Correct flags detailing the type of error occurrence. These are gen- The probability of double bit errors in DRAM systems is rela- erated using the syndrome word in the manner shown in tively low, but as memory array sizes grow, the occurrence Figure 11. The resulting error type identifications are shown of these error types must be considered. Adopting certain in Table V. The three error flags allow complete error type pr
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After the complement correct cycle, the memory must be ice. Using this technique, software may be provided in the rewritten with the corrected data since the address now system to warn the operator that the system is in a degrad- contains data that is complemented. Full error reporting is ed operational mode and that field service should occur available from the DP8400 after the second read, the com- shortly. In the meantime, the system will continue to operate properly. The key to the effective
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MICROPROCESSOR INTERFACE CIRCUITS This system structure requires the insertion of few or no wait states during a memory access cycle, thus maximizing The major 8-bit, 16-bit and 32-bit microprocessors have dif- throughput. The DP84XX2 circuits have been designed to ferent control signal timing. There are also a number of work with all of National's DRAM controller/drivers to con- speed options. The DP8400 family was designed, not for a trol refreshing so that system throughput is affected only s
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The DP8400 DRAM interface family provides complete solu- for universal applications with multiple microprocessors, tions to memory support. This begins with the LSI functions with no manufacturers CPU enjoying a favorite role. such as the DP8400 expandable error checker/corrector Data sheets and more detailed application information are and the DP8409A DRAM controller/driver. It continues with available for all the members of the DP8400 family. Contact the DP84240 and the DP84244 high performanc
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LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose b
