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MVME2300 Series
VME Processor Module
Programmer’s Reference
Guide
V2300A/PG5
Edition of June 2001
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© Copyright 2001 Motorola, Inc. All rights reserved. Printed in the United States of America. ® Motorola and the Motorola logo are registered trademarks of Motorola, Inc. ® PowerPC is a registered trademark of International Business Machines Corporation and is used by Motorola with permission. All other products mentioned in this document are trademarks or registered trademarks of their respective holders.
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Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessa
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Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not ! installed and used with adequate EMI protection. Caution Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry. Danger of explosion if battery i
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CE Notice (European Community) Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this directive implies conformity to the following European Norms: EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment”; this product tested to Equipment Class B EN50082-1:1997 “Electromagnetic Compatibility—Generic Immunity Standard, Part 1. Residential, Commercial and Light Industry”
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Limited and Restricted Rights Legend If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFA
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Contents About This Manual Summary of Changes.................................................................................................. xx Overview of Contents ................................................................................................xxi Comments and Suggestions .......................................................................................xxi Conventions Used in This Manual............................................................................xxii CHAP
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CPU Control Register ............................................................................... 1-30 ISA Local Resource Bus.......................................................................................... 1-31 W83C553 PIB Registers .................................................................................. 1-31 16550 UART .................................................................................................... 1-31 General-Purpose Readable Jumpers.................
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PCI Master.................................................................................................2-17 Generating PCI Cycles ..............................................................................2-21 Endian Conversion............................................................................................2-25 When MPC Devices are Big-Endian .........................................................2-25 When MPC Devices are Little-Endian ........................................
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Nesting of Interrupt Events ....................................................................... 2-62 Spurious Vector Generation...................................................................... 2-62 Interprocessor Interrupts (IPI)................................................................... 2-62 8259 Compatibility.................................................................................... 2-62 Raven-Detected Errors ...........................................................
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8259 Mode.................................................................................................2-90 Current Task Priority Level.......................................................................2-90 Architectural Notes ...........................................................................................2-91 CHAPTER 3 Falcon ECC Memory Controller Chip Set Introduction..............................................................................................................
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DRAM Attributes Register ....................................................................... 3-33 DRAM Base Register................................................................................ 3-35 CLK Frequency Register........................................................................... 3-35 ECC Control Register ............................................................................... 3-36 Error Logger Register ...............................................................
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Universe Chip Problems after PCI Reset..........................................................4-14 Description.................................................................................................4-14 Workarounds .............................................................................................4-15 Examples...........................................................................................................4-16 Example 1: MVME2600 Series Board Exhibits PCI Reset Prob
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List of Figures Figure 1-1. MVME2300 Series System Block Diagram ...........................................1-5 Figure 1-2. VMEbus Master Mapping.....................................................................1-20 Figure 1-3. VMEbus Slave Mapping .......................................................................1-22 Figure 1-4. General-Purpose Software-Readable Header........................................1-32 Figure 2-1. Raven Block Diagram ...........................................
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List of Tables Table 1-1. Features: MVME2300 Series....................................................................1-2 Table 1-2. Default Processor Memory Map...............................................................1-8 Table 1-3. CHRP Memory Map Example..................................................................1-9 Table 1-4. Raven MPC Register Values for CHRP Memory Map...........................1-10 Table 1-5. PREP Memory Map Example.............................................
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Table 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper Devices ........... 3-9 Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing — 64 Bits (32 Bits per Falcon) ................................................................................................. 3-10 Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing — 16 Bits (8 Bits per Falcon)............................................................................................................... 3-10 Table 3-7. Error Reporting....
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About This Manual The MVME2300 Series VME Processor Module Programmer’s Reference Guide provides board-level information and detailed ASIC information, including register bit descriptions, for the MVME2300 and MVME2300SC series of VME processor modules. The MVME2300 series VME processor module is based on an MPC603 or MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O. In addition, the MVME2300SC versions of the board give both PM
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This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in Appendix A, Related Documentation. Summary of Changes This is the fifth edition of the Programmer’s Reference Guide. It supersedes the March 2001 edition and incorporates the fo
