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®
TigerSHARC
Embedded Processor
a
ADSP-TS201S
KEY FEATURES KEY BENEFITS
Up to 600 MHz, 1.67 ns instruction cycle rate Provides high performance static superscalar DSP
operations, optimized for telecommunications
24M bits of internal—on-chip—DRAM memory
infrastructure and other large, demanding multiprocessor
25 mm × 25 mm (576-ball) thermally enhanced ball grid
DSP applications
array package
Performs exceptionally well on DSP algorithm and I/O
Dual-computation blocks—each containing an AL
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ADSP-TS201S TABLE OF CONTENTS General Description ................................................. 3 Test Conditions .................................................. 37 Dual Compute Blocks ............................................ 4 Output Disable Time ......................................... 37 Data Alignment Buffer (DAB) .................................. 4 Output Enable Time ......................................... 38 Dual Integer ALU (IALU) ....................................... 4 C
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ADSP-TS201S GENERAL DESCRIPTION The ADSP-TS201S TigerSHARC processor is an ultrahigh per- • An interrupt controller that supports hardware and soft- formance, static superscalar processor optimized for large signal ware interrupts, supports level- or edge-triggers, and processing tasks and communications infrastructure. The DSP supports prioritized, nested interrupts combines very wide memory widths with dual computation • Four 128-bit internal data buses, each connecting to the six blocks—su
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ADSP-TS201S TM† The TigerSHARC DSP uses a Static Superscalar architecture. storing intermediate results. Instructions can access the This architecture is superscalar in that the ADSP-TS201S pro- registers in the register file individually (word-aligned), in cessor’s core can execute simultaneously from one to four 32-bit sets of two (dual-aligned), or in sets of four (quad-aligned). instructions encoded in a very large instruction word (VLIW) • ALU—the ALU performs a standard set of arithmeti
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ADSP-TS201S The IALUs have hardware support for circular buffers, bit The DSP distinguishes between hardware interrupts and soft- reverse, and zero-overhead looping. Circular buffers facilitate ware exceptions, handling them differently. When a software efficient programming of delay lines and other data structures exception occurs, the DSP aborts all other instructions in the required in digital signal processing, and they are commonly instruction pipe. When a hardware interrupt occurs, the D
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ADSP-TS201S GLOBAL SPACE 0xFFFFFFFF HOST(MSH) 0x80000000 RESERVED 0x74000000 MSSDBANK3(MSSD3) 0x70000000 RESERVED INTERNALSPACE 0x64000000 0x03FFFFFF MSSDBANK2 (MSSD2) 0x60000000 RESERVED 0x54000000 MSSDBANK1(MSSD1) 0x50000000 RESERVED RESERVED 0x44000000 MSSDBANK0(MSSD0) 0x40000000 BANK1 (MS1) 0x001F03FF 0x38000000 SOC REGISTERS (UREGS) 0x001F0000 BANK0 (MS0) RESERVED 0x001E03FF 0x30000000 INTERNAL REGISTERS (UREGS) PROCESSOR ID 7 0x001E0000 0x2C000000 RESERVED PROCESSOR ID 6 0x0015FFFF 0x28000
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ADSP-TS201S The ADSP-TS201S processor provides programmable memory, The DSP’s four link ports provide a second path for interproces- pipeline depth, and idle cycle for synchronous accesses; and sor communications with throughput of 4G bytes per second. external acknowledge controls to support interfacing to pipe- The cluster bus provides 1G byte per second throughput—with lined or slow devices, host processors, and other memory- a total of 4.8G bytes per second interprocessor bandwidth (lim- m
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ADSP-TS201S ADSP-TS201S #7 ADSP-TS201S #6 ADSP-TS201S #5 ADSP-TS201S #4 ADSP-TS201S #3 ADSP-TS201S #2 ADSP-TS201S #1 001 ID2–0 BR7–2,0 RST_IN BR1 ADDR31–0 CLKS/REFS DATA31–0 LINK LINK CONTROL DEVICES ADSP-TS201S #0 000 ID2–0 BR7–1 BR0 RESET RST_IN ADDR31–0 ADDR GLOBAL DATA31–0 CLKS/REFS DATA MEMORY RST_OUT RD OE AND POR_IN PERIPHERALS WRL WE (OPTIONAL) CLOCK SCLK ACK ACK MS1–0 CS BUSLOCK BMS CS BOOT CPA ADDR REFERENCE SCLK_V EPROM REF DPA (OPTIONAL) V DATA REFERENCE REF BRST SCLKRAT2–0 CLOCK DMA
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ADSP-TS201S After reset, the ADSP-TS201S processor has four boot options LINK PORTS (LVDS) for beginning operation: The DSP’s four full-duplex link ports each provide additional • Boot from EPROM. four-bit receive and four-bit transmit I/O capability, using low voltage, differential-signal (LVDS) technology. With the ability • Boot by an external master (host or another ADSP-TS201S to operate at a double data rate—latching data on both the rising processor). and falling edges of the clock—
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ADSP-TS201S The VisualDSP++ project management environment lets pro- POWER DOMAINS grammers develop and debug an application. This environment The ADSP-TS201S processor has separate power supply con- includes an easy to use assembler (which is based on an alge- nections for internal logic (V ), analog circuits (V ), I/O DD DD_A braic syntax), an archiver (librarian/library builder), a linker, a buffer (V ), and internal DRAM (V ) power supply. DD_IO DD_DRAM loader, a cycle-accurate instructio
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ADSP-TS201S eliminating the need to start from the very beginning when are sample application programs, power supply, and a USB developing new application code. The VDK features include cable. All evaluation versions of the software tools are limited threads, critical and unscheduled regions, semaphores, events, for use only with the EZ-KIT Lite product. and device flags. The VDK also supports priority-based, pre- The USB controller on the EZ-KIT Lite board connects the emptive, cooperative,
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ADSP-TS201S PIN FUNCTION DESCRIPTIONS While most of the ADSP-TS201S processor’s input pins are nor- The output pins can be three-stated during normal operation. mally synchronous—tied to a specific clock—a few are The DSP three-states all output pins during reset, allowing these asynchronous. For these asynchronous signals, an on-chip syn- pins to get to their internal pull-up or pull-down state. Some chronization circuit prevents metastability problems. Use the ac pins have an internal pull-
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ADSP-TS201S Table 5. Pin Definitions—External Port Bus Controls Signal Type Term Description ADDR31–0 I/O/T nc Address Bus. The DSP issues addresses for accessing memory and peripherals on (pu_ad) these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS201S processors. The DSP inputs addresses when a host or another DSP accesses its internal memory or I/O processor registers. DATA63–0 I/O/T nc External
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ADSP-TS201S Table 6. Pin Definitions—External Port Arbitration Signal Type Term Description 1 BR7–0 I/O V Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to DD_IO arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight pins high (V ). DSPs, set the unused BRx DD_IO ID2–0 I (pd) na Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determ
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ADSP-TS201S Table 7. Pin Definitions—External Port DMA/Flyby Signal Type Term Description DMAR3–0 I/A epu DMA Request Pins. Enable external I/O devices to request DMA services from the DSP. In response to DMARx, the DSP performs DMA transfers according to the DMA channel’s initialization. The DSP ignores DMA requests from uninitialized channels. IOWR O/T nc I/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP (pu_0) asserts the IOWR signal during the data cycles
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ADSP-TS201S Table 8. Pin Definitions—External Port SDRAM Controller Signal Type Term Description MSSD3–0 I/O/T nc Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the (pu_0) DSP accesses SDRAM memory space. MSSD3–0 are decoded memory address pins that are asserted whenever the DSP issues an SDRAM command cycle (access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 3 on Page 6). In a multi- processor system, the master DSP drives MSSD3–0. RAS I/O/T nc Row Ad
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ADSP-TS201S Table 9. Pin Definitions—JTAG Port Signal Type Term Description 1 EMU O/OD nc Emulation. Connected to the DSP’s JTAG emulator target board connector only. 1 TCK I epd or epu Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. 1 TDI I (pu_ad) nc Test Data Input (JTAG). A serial data input of the scan path. 1 TDO O/T nc Test Data Output (JTAG). A serial data output of the scan path. 1 TMS I (pu_ad) nc Test Mode Select (JTAG). Used to control the test state machine. TRST I
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ADSP-TS201S Table 11. Pin Definitions—Link Ports Signal Type Term Description LxDATO3–0P O nc Link Ports 3–0 Data 3–0 Transmit LVDS P LxDATO3–0N O nc Link Ports 3–0 Data 3–0 Transmit LVDS N LxCLKOUTP O nc Link Ports 3–0 Transmit Clock LVDS P LxCLKOUTN O nc Link Ports 3–0 Transmit Clock LVDS N LxACKI I (pd) nc Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the transmitter that it may continue the transmission. LxBCMPO O (pu) nc Link Ports 3–0 Block Completion.
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ADSP-TS201S Table 13. Impedance Control Selection CONTROLIMP1-0 Driver Mode 00 (recommended) Normal 01 Reserved 10 (default) A/D Mode 11 Reserved Table 14. Drive Strength/Output Impedance Selection DS2–0 Drive Output 1 2 Pins Strength Impedance 000 Strength 0 (11.1%) 26 Ω 001 Strength 1 (23.8%) 32 Ω 010 Strength 2 (36.5%) 40 Ω 011 Strength 3 (49.2%) 50 Ω 100 Strength 4 (61.9%) 62 Ω 101 (default) Strength 5 (74.6%) 70 Ω 110 Strength 6 (87.3%) 96 Ω 111 Strength 7 (100%) 120 Ω 1 CONTROLIMP1 = 0,
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ADSP-TS201S STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate functions at reset. Strap options set connected to logic inputs, a stronger external pull-up or pull- DSP operating modes. During reset, the DSP samples the strap down may be required to ensure default value depending on option pins. Strap pins have an internal pull-up or pull-down leakage and/or low level input current of the logic load. To set a for the default value. If a strap pin is not connected to an over- mode other t
