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®
Intel E8500 Chipset North
Bridge (NB) and eXternal Memory
Bridge (XMB)
Thermal/Mechanical Design Guide
March 2005
Document Number 306749-001
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents 1 Introduction.........................................................................................................................7 1.1 Design Flow .........................................................................................................................7 1.2 Definition of Terms...............................................................................................................8 1.3 Reference Documents .......................................................
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8.5 XMB Heatsink Thermal Solution Assembly....................................................................... 38 8.5.1 Heatsink Orientation ........................................................................................... 39 8.5.2 Extruded Heatsink Profiles ................................................................................. 40 8.5.3 Mechanical Interface Material............................................................................. 40 8.5.4 Thermal Interface Mat
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Tables ® 3-1 Intel E8500 Chipset NB Thermal Specifications ..............................................................15 ® 3-2 Intel E8500 Chipset XMB Thermal Specifications ...........................................................16 6-1 Chomerics THERMFLOW* T710 TIM Performance as a Function of Attach Pressure .....28 6-2 Reliability Guidelines..........................................................................................................29 A-1 NB Heatsink Thermal Solution #1....
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Revision History Document Revision Description Date Number Number 306749 001 • Initial release of this document March 2005 NOTE: Not all revisions may be published. § ® 6 Intel E8500 Chipset North Bridge (NB) and eXternal Memory Bridge (XMB) Thermal/Mechanical Design Guide
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1 Introduction As the complexity of computer systems increases, so do the power dissipation requirements. Care must be taken to ensure that the additional power is properly dissipated. Typical methods to improve heat dissipation include selective use of ducting, and/or passive heatsinks. The goals of this document are to: ® • Outline the thermal and mechanical operating limits and specifications for the Intel E8500 ® chipset North Bridge (NB) component and the Intel E8500 chipset eXternal Mem
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Introduction Figure 1-1. Thermal Design Process 001239 1.2 Definition of Terms BGA Ball grid array. A package type, defined by a resin-fiber substrate, onto which a die is mounted, bonded and encapsulated in molding compound. The primary electrical interface is an array of solder balls attached to the substrate opposite the die and molding compound. BLT Bond line thickness. Final settled thickness of the thermal interface material after installation of heatsink. ICH5 I/O controller hub. The
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Introduction ® XMB Intel E8500 chipset eXternal Memory Bridge Component. The chipset component that bridges the IMI and DDR interfaces. 1.3 Reference Documents The reader of this specification should also be familiar with material and concepts presented in the following documents: ® ® • Intel 82801EB I/O Controller Hub 5 (ICH5) and Intel 82801ER I/O Controller Hub 5 R (ICH5R) Thermal Design Guide ® ® • Intel 82801EB I/O Controller Hub 5 (ICH5) and Intel 82801ER I/O Controller Hub 5 R (ICH5R)
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Introduction ® 10 Intel E8500 Chipset North Bridge (NB) and eXternal Memory Bridge (XMB) Thermal/Mechanical Design Guide
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2 Packaging Technology ® The E8500 chipsets consist of four individual components: the NB, the XMB, the Intel 6700PXH 64-bit PCI Hub and the I/O controller hub (ICH5r). The E8500 chipset NB component use a 42.5 mm squared, 12-layer flip chip ball grid array (FC-BGA) package (see Figure 2-1 through Figure 2-3). The E8500 chipset XMB component uses a 37.5mm squared, 10-layer FB-BGA package (see Figure 2-4 through Figure 2-6). For information on the Intel 6700PXH 64-bit PCI ® Hub package, refe
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Packaging Technology Figure 2-3. NB Package Dimensions (Bottom View) AV A U AT A R AP A N AM AL AK AJ A H AG AF AE A D A C AB AA Y W 42.5 + 0.05 V U T R P N M L 20.202 K J H G F E 37X 1.092 D C B A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 A 37X 1.092 20.202 42.5 + 0.05 B 0.2 C A NOTES: 1. All dimensions are in millimeters. 2. All dimensions and tolerances conform to ANSI Y14.5M-1994. ® 12 Intel 8500 Chipset North Bridge (NB) and eXt
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Packaging Technology Figure 2-4. XMB Package Dimensions (Top View) Die Handling Keepout Exclusion Area 14.02mm. Area 8.88mm. XMB 11.73mm. 6.65mm. 23.50mm. 27.50mm. 37.50mm. Die 23.50mm. 27.50mm. 37.50mm. Figure 2-5. XMB Package Dimensions (Side View) Substrate Decoup 2.535 ± 0.123 mm Die Cap 2.100 ± 0.121 mm 0.84 ± 0.05 mm 0.7 mm Max 0.20 See Note 4 0.20 –C– Seating Plane 0.435 ± 0.025 mm See Note 3 See Note 1 Notes: 1. Primary datum -C- and seating plan are defined by the spherical crowns of t
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Packaging Technology Figure 2-6. XMB Package Dimensions (Bottom View) AV A U AT A R AP A N AM AL AK AJ A H AG AF AE A A D C AB AA Y W 42.5 + 0.0 V U T R P N M L 20.202 K J H G F E 37X 1.092 D C B A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 A 37X 1.092 20.202 42.5 + 0.05 B 0.2 C A 2.1 Package Mechanical Requirements The E8500 chipset NB package has an IHS and the XMB package has an exposed bare die which is capable of sustaining a ma
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3 Thermal Specifications 3.1 Thermal Design Power (TDP) Analysis indicates that real applications are unlikely to cause the E8500 chipset NB/XMB components to consume maximum power dissipation for sustained time periods. Therefore, in order to arrive at a more realistic power level for thermal design purposes, Intel characterizes power consumption based on known platform benchmark applications. The resulting power consumption is referred to as the Thermal Design Power (TDP). TDP is the targe
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Thermal Specifications ® Table 3-2. Intel E8500 Chipset XMB Thermal Specifications Parameter Value Notes T 105°C case_max T 5°C case_min TDP 9.1W DDR-266 dual channel TDP 9.3W DDR-333 dual channel TDP 8.5W DDR2-400 dual channel NOTE: 1. These specifications are based on silicon characterization, however, they may be updated as further data becomes available. § ® 16 Intel E8500 Chipset North Bridge (NB) and eXternal Memory Bridge (XMB) Thermal/Mechanical Design Guide
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4 Thermal Simulation Intel provides thermal simulation models of the E8500 chipset NB/XMB components and associated user's guides to aid system designers in simulating, analyzing, and optimizing their thermal solutions in an integrated, system-level environment. The models are for use with the commercially available Computational Fluid Dynamics (CFD)-based thermal analysis tool FLOTHERM* (version 3.1 or higher) by Flomerics, Inc. These models are also available in ICEPAK* format. Contact yo
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Thermal Simulation ® 18 Intel E8500 Chipset North Bridge (NB) and eXternal Memory Bridge (XMB) Thermal/Mechanical Design Guide
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5 Thermal Metrology The system designer must make temperature measurements to accurately determine the thermal performance of the system. Intel has established guidelines for proper techniques to measure the NB/XMB die temperatures. Section 5.1 provides guidelines on how to accurately measure the NB/XMB die temperatures. Section 5.2 contains information on running an application program that will emulate anticipated maximum thermal design power. The flowchart in Figure 5-1 offers useful gui
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Thermal Metrology Figure 5-1. Thermal Solution Decision Flowchart 001240 Figure 5-2. Zero Degree Angle Attach Heatsink Modifications NOTE: Not to scale. Figure 5-3. Zero Degree Angle Attach Methodology (Top View) Die Thermocouple Wire Cement + Thermocouple Bead Substrate 001321 NOTE: Not to scale. ® 20 Intel E8500 Chipset North Bridge (NB) and eXternal Memory Bridge (XMB) Thermal/Mechanical Design Guide
