Summary of the content on the page No. 1
AMD Geode™ SC2200 Processor
Data Book
March 2006
Publication ID: 32580B
AMD Geode™ SC2200 Processor Data Book
Summary of the content on the page No. 2
© 2006 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property
Summary of the content on the page No. 3
Contents 32580B Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 4
32580B Contents 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.2 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 5
List of Figures 32580B List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3-2. BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 4-1. WATCHDOG Block
Summary of the content on the page No. 6
32580B List of Figures Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer . . . . . . . . . . . . . . . . . . 325 Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers . . . . . . . . . . . . . . . 326 Figure 7-7. Video Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Figure 7-8. Horizontal Downscaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 7
List of Figures 32580B Figure 9-45. ECP Forward Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Figure 9-46. ECP Reverse Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Figure 9-47. AC97 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Figure 9-48. AC97 Sync Timing Diagram . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 8
32580B List of Figures 8 AMD Geode™ SC2200 Processor Data Book
Summary of the content on the page No. 9
List of Tables 32580B List of Tables Table 2-1. SC2200 Memory Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC2200 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 3-1. Signal Definitions Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number . .
Summary of the content on the page No. 10
32580B List of Tables Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map . . . . . . . . . . . . . . . . . . . . 124 Table 5-29. Banks 0 and 1 - Common Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 126 Table 5-31. ACB Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the content on the page No. 11
List of Tables 32580B Table 6-21. F2BAR4: IDE Controller Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 6-22. F3: PCI Header Registers for Audio Support Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 6-23. F3BAR0: Audio Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary . . . . . . . . . . . . . . . .
Summary of the content on the page No. 12
32580B List of Tables Table 9-9. Balls with PU/PD Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Table 9-10. PLL4 (48 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Table 9-11. PLL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Table 9-12. PLL6 (57.273 MHz) . .
Summary of the content on the page No. 13
Overview 32580B 1.0Overview 1 1.1 General Description The AMD Geode™ SC2200 processor is a member of the � The Core Logic module includes: PC/AT functionality, a AMD Geode processor family of fully integrated x86 system USB interface, an IDE interface, a PCI bus interface, an chips. The SC2200 processor includes: LPC bus interface, Advanced Configuration Power Inter- face (ACPI) version 1.0 compliant power management, � The Geode GX1 processor module combines advanced and an audio codec inte
Summary of the content on the page No. 14
32580B Overview 1.2 Features General Features Video Processor Module ■ 32-Bit x86 processor, up to 300 MHz, with MMX ■ Video Accelerator: instruction set support — Flexible video scaling support of up to 8x (horizontally and vertically) ■ Memory controller with 64-bit SDRAM interface — Bilinear interpolation filters (with two taps, and eight ■ 2D graphics accelerator phases) to smooth output video ■ Video/Graphics Mixer: ■ CRT controller with hardware video accelerator — 8-bit value alpha blen
Summary of the content on the page No. 15
Overview 32580B ■ General Purpose I/Os (GPIOs): Other Features — 27 multiplexed GPIO signals ■ High-Resolution Timer: ■ Low Pin Count (LPC) Bus Interface: — 32-Bit counter with 1 μs count interval — Specification v1.0 compatible ■ WATCHDOG Timer: ■ PCI Bus Interface: — Interfaces to INTR, SMI, Reset — PCI v2.1 compliant with wakeup capability ■ Clocks: — 32-Bit data path, up to 33 MHz — Input (external crystals): — Glueless interface for an external PCI device – 32.768 KHz (internal clock oscill
Summary of the content on the page No. 16
32580B Overview 16 AMD Geode™ SC2200 Processor Data Book
Summary of the content on the page No. 17
Architecture Overview 32580B 2.0Architecture Overview 2 As illustrated in Figure 1-1 on page 13, the SC2200 pro- The device ID of the SC2200 processor is contained in the cessor contains the following modules in one integrated GX1 module. Software can detect the revision by reading device: the DIR0 and DIR1 Configuration registers (see Configura- tion registers in the AMD Geode™ GX1 Processor Data � GX1 Module: Book). The AMD Geode™ SC2200 Processor Specifica- — Combines advanced CPU performance
Summary of the content on the page No. 18
32580B Architecture Overview Table 2-1. SC2200 Memory Controller Register Summary GX_BASE+ Width Memory Offset (Bits) Type Name/Function Reset Value 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C0040h 8404h-8407h 32 R/W MC_MEM_CNTRL2. Memory Controller Control Register 2 00000801h 8408h-840Bh 32 R/W MC_BANK_CFG. Memory Controller Bank Configuration 41104110h 840Ch-840Fh 32 R/W MC_SYNC_TIM1. Memory Controller Synchronous Timing 2A733225h Register 1 8414h-8417h 32 R/W
Summary of the content on the page No. 19
Architecture Overview 32580B Table 2-2. SC2200 Memory Controller Registers (Continued) Bit Description 5 2CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted. 0: Disable. 1: Enable. This can be used to compensate for address setup at high frequencies and/or high loads. 4 RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes. 3 XBUSARB (X-Bus Round Robin). When round robin is enabl
Summary of the content on the page No. 20
32580B Architecture Overview Table 2-2. SC2200 Memory Controller Registers (Continued) Bit Description GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset Value: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM for SODIMM: 0: 1 Module bank (Bank 0 only). 1: 2 Module banks (Bank 0 and 1). 13 RSVD (Reserved). Write as 0. 12 SODIMM_COMP_BNK (SODIMM Component Banks -
