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AMD Geode™ LX Processor
DDR2 BIOS Porting Guide
1.0 Scope
The AMD Geode™ LX processor has an integrated DDR Table 2-1. Initialization Steps
memory controller. Due to the concerns over the availability
DDR DDR2
and increasing cost of DDR, AMD has developed a method
for operating DDR2 memory with the processor’s memory
Wait a minimum of 200µs Wait a minimum of 200µs
controller. This application note details the software
after clocks and power are after clocks and power are
changes necessary to
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Application Note 46959A - March 2009 3.0 Solution The method for initializing DDR2 memory on the processor Because the CPLD is contained on the DIMM assembly, is to insert a CPLD and quick switches in the address and the only bus available for communication is I2C. The BA signals. Figure 3-1 shows a block diagram of this CPLD’s I2C address is A0/A1 (i.e., the same as DIMM0). design. During initialization, the Enable signal opens The CPLD also contains the SPD information. (default) the switches.
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Application Note 46959A - March 2009 3.2 CPLD Registers The CPLD contains two registers that indicate how it Prior to executing a LOAD MODE command, the BIOS sets should assert the BA[1:0], A[12:0] signals and switch the CPLD registers to the desired pattern. The DRAM reg- enable signals. isters are programmed with the A[n] signals. The register being initialized is determined by the pattern on BA[1:0] � If accessing the registers via I2C, the register addresses (MR=00b, EMR(1)=01b, EMR(2)=10b
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Application Note 46959A - March 2009 3.3 Initialization Steps Some of the following steps may be optional, depending on Calculate the size of each DIMM. SPD[31] indicates the specific implementation. The reader is encouraged to the density of each rank and it is defined differently have a copy of the JEDEC standard for DDR2 SDRAM, than in the DDR specification. Multiply this by the num- including the SPD byte definitions. The AMD Geode™ LX ber of ranks from SPD[5] to find the DIMM size. This Pro
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Application Note 46959A - March 2009 cally supportable. As an example, consider the follow- 3.3.2 SDRAM Initialization ing DIMM characteristics: 1) CKE may have already been asserted, due to the requirement of the On-DIMM CPLD. If not, assert CKE CAS# Min Cycle Max Cycle by clearing the MASK_CKEn bit(s) in the Latency Time (ns) Time (ns) MC_CFCLK_DBUG register. CKE needs to be CL=5 3.0 8.0 asserted for at least 400ns before executing step 2. CL=4 3.75 8.0 Also, set REF_STAG in MC_CF07_DATA to
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Application Note 46959A - March 2009 the CPLD are typically 0. Set SW_EN# high and 11) Issue a LOAD MODE command to EMR(1) to exit BA[1:0] to 01b. OCD programming. A[1:0] (driver strength and DLL enable) are retrieved from MC_CF07_DATA. Set Next, in MC_CF07_DATA register, set MSR_BA=01b A[9:7]=000b for OCD default. Set SW_EN#=1 and and PROG_DRAM=1. Then clear PROG_DRAM. BA[1:0]=01b. In MC_CF07_DATA set MSR_BA=01b 6) Issue a LOAD MODE command to MR to reset the and PROG_DRAM=1. Then clear PROG_DR
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Application Note 46959A - March 2009 3.4 Other Information and Restrictions The LX processor/DDR2 solution does not do DQS train- Supporting CL=2 at higher frequencies implies that the ing. The LX processor’s memory controller does not have memory must be of higher performance. To run the mem- the adjustability to make this worthwhile, and the speeds ory at 166MHz, this means that the memory should have are slow enough that this is not a problem. an access time of 12ns. 133MHz requires 15ns. Th
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© 2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property
