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ADS61xx and ADS61B23EVM
User's Guide
Literature Number: SLAU206B
September 2007–Revised April 2008
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2 SLAU206B–September 2007–Revised April 2008 Submit Documentation Feedback
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Contents 1 Overview............................................................................................................................. 5 1.1 ADS61xx/ADS61B23 EVM Quick-Start Procedure ................................................................... 5 2 Circuit Description ............................................................................................................... 6 2.1 Schematic Diagram...............................................................................
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www.ti.com List of Figures 1 TI ADC SPC Interface Screen ........................................................................................... 10 2 Top Silkscreen.............................................................................................................. 16 3 Component Side............................................................................................................ 17 4 Ground Plane 1..........................................................................
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User's Guide SLAU206B–September 2007–Revised April 2008 1 Overview This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6122, ADS6123, ADS6124, ADS6125, ADS6142, ADS6143, ADS6144, ADS6145, and ADS61B23, which collectively are referred to as ADS61xx and ADS61B23. The ADS61xx/ADS61B23 EVM provides a platform for evaluating the low-power
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Circuit Description www.ti.com 2 Circuit Description 2.1 Schematic Diagram The schematic diagram for the EVM is in Section 6.3. 2.2 ADC Circuit Function The following sections describe the function of individual circuits. See the relevant data sheet for device operating characteristics. 2.2.1 ADC Operational Mode By default, the ADC is configured to operate in parallel-mode operation, because jumper (J3) asserts a 3.3-V state to the ADC reset pin. Consequently, the SW1 reset pushbutton must be p
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www.ti.com Circuit Description Note that the THS4509 used on this EVM is pinout compatible with the THS4508, THS4511, THS4513, and THS4520. Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier based on common-mode range, power supplies, and frequency of operation. Contact your local Texas Instruments (TI) sales representative for assistance in selection of these amplifiers. 2.2.4 ADC Clock Input Connect a filtered, low-phase-noise clock input to J9. A transfo
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Circuit Description www.ti.com Table 1. Breakout Board Pin Assignments ADS6122/23/B23/24/25 J4 PIN ADS6142/43/44/45 DESCRIPTION DESCRIPTION 1 GND GND 2 CLK CLK 3 GND GND 4 NC NC 5 GND GND 6 NC Data bit 0 (LSB) 7 GND GND 8 NC Data bit 1 9 GND GND 10 Data bit 0 (LSB) Data bit 2 11 GND GND 12 Data bit 1 Data bit 3 13 GND GND 14 Data bit 2 Data bit 4 15 GND GND 16 Data bit 3 Data bit 5 17 GND GND 18 Data bit 4 Data bit 6 19 GND GND 20 Data bit 5 Data bit 7 21 GND GND 22 Data bit 6 Data bit 8 23 GND
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www.ti.com Circuit Description Table 2. Jumpers Description Reference Designator Default Selection Optional Selection Parallel mode: SEN pin J1 5–6, Offset binary, CMOS output Multiple choices voltage bias SEN control J2 2–3, EVM controlled 1–2, USB or FPGA controlled ADC control mode J3 2–3, Parallel mode 1–2, serial mode Parallel mode: SCLK pin J4 1–2, 0-dB Gain, Int Ref Multiple choices voltage bias ADS61xx/ADS61B23 J5 1–2, ADS61xx/ADS61B23 powered on 2–3, ADS61xx/ADS61B23 power down powered
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TI ADC SPI Control Interface www.ti.com 3 TI ADC SPI Control Interface This section describes the software features accompanying the EVM kit. The TI ADC SPI control software provides full control of the SPI interface, allowing users to write to any of the ADC registers found in the ADC data sheet. For most ADS61xx/ADS61B23 performance evaluations, users do not need to use the TI SPI control software to get evaluation results. Users only need to use the ADC SPI control software when the desired f
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www.ti.com TI ADC SPI Control Interface 3.2 Setting Up the EVM for ADC SPI Control Users who wish to use the ADC SPI interface must supply 5 VDC to J20, which provides power to the USB circuit. By default, the EVM comes with the ADC configured in parallel mode. In order to use the SPI interface to control the ADC modes of operation, users must move several jumpers. • Move jumper J3 to short positions 1–2, which places the ADC into serial operation mode. • Move jumper J7 to short positions 1–2, w
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TI ADC SPI Control Interface www.ti.com Table 4. ADS61xx Frequently Used Registers Default Value Alternate Value ADS61xx Reset 2s Complement Straight Binary CMOS DDR LVDS Powerdown: OFF Powerdown On No Course Gain 3.5-dB Course Gain INT Reference EXT Reference Bit-Wise (LVDS Only) Byte-Wise Test Mode: None Multiple Options 12 SLAU206B–September 2007–Revised April 2008 Submit Documentation Feedback
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www.ti.com Connecting to FPGA Platforms 4 Connecting to FPGA Platforms The ADS61xx/ADS61B23 EVM provides several connection options to mate the EVM to various FPGA development platforms and FPGA-based capture boards. 4.1 TSW1100 Using the accompanying CMOS breakout board, users can easily mate TI's TSW1100 capture board to the ADS61xx/ADS61B23 EVM. Simply connect the breakout board to the J2 (Channel 2) connector on the TSW1100. From an orientation standpoint, the Xilinx™ FPGA faces the ADC when
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ADC Evaluation www.ti.com 5 ADC Evaluation This section describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for data-sheet generation. Consequently, the information in this section is generic in nature and is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal tone analysis, which yields ADC data-sheet figures of merit such as signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). 5.1 Hardwa
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www.ti.com ADC Evaluation 5.2 Coherent Input Frequency Selection Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is impractical when looking at a finite set of ADC samples, usually collected from a logic analyzer. Consequently, users typically apply a window function to minimize the time-domain
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Physical Description www.ti.com 6 Physical Description This section describes the physical characteristics and PCB layout of the EVM. 6.1 PCB Layout The EVM is constructed on a four-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 2 through Figure 6. The layout features a split ground plane; however, similar performance can be obtained with careful layout using a common ground plane. Figure 2. Top Silkscreen 16 SLAU206B–September 2007–Revised April 2008
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www.ti.com Physical Description Figure 3. Component Side SLAU206B–September 2007–Revised April 2008 17 Submit Documentation Feedback
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Physical Description www.ti.com Figure 4. Ground Plane 1 18 SLAU206B–September 2007–Revised April 2008 Submit Documentation Feedback
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www.ti.com Physical Description Figure 5. Power Plane 1 SLAU206B–September 2007–Revised April 2008 19 Submit Documentation Feedback
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Physical Description www.ti.com Figure 6. Bottom Side 20 SLAU206B–September 2007–Revised April 2008 Submit Documentation Feedback
