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REJ09B0126-0102
M16C/6N Group
(M16C/6NL, M16C/6NN)
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/60 SERIES
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Rev. 1.02
Revision date: Jul. 01, 2005 www.renesas.com
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Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- fl
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How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 0 0 Symbol Address After Reset *5 XXX XXX 00h Bit Bit Name Function RW Symbol b1b0 *2 XXX0 0 0: XXX
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3. M16C Family Documents (1) The following documents were prepared for the M16C family . Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note • Application examples of periphe
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Table of Contents SFR Page Reference ............................................................................................................ B-1 1. Overview ............................................................................................................................... 1 1.1 Applications ..................................................................................................................................................1 1.2 Performance Outline ...................
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7.2 CPU Clock and Peripheral Function Clock ................................................................................................ 43 7.2.1 CPU Clock and BCLK ........................................................................................................................43 7.2.2 Peripheral Function Clock ..................................................................................................................43 7.3 Clock Output Function .................................
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11. DMAC ................................................................................................................................ 78 11.1 Transfer Cycle ..........................................................................................................................................83 11.1.1 Effect of Source and Destination Addresses .................................................................................... 83 11.1.2 Effect of Software Wait .............................
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18. CAN Module .................................................................................................................... 198 18.1 CAN Module-Related Registers ............................................................................................................. 199 18.1.1 CAN Message Box......................................................................................................................... 199 18.1.2 Acceptance Mask Registers....................................
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20.4 Standard Serial I/O Mode ......................................................................................................................256 20.4.1 ID Code Check Function ................................................................................................................256 20.4.2 Example of Circuit Application in Standard Serial I/O Mode .......................................................... 260 20.5 Parallel I/O Mode ..................................................
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22.18 Flash Memory Version ......................................................................................................................... 308 22.18.1 Functions to Prevent Flash Memory from Rewriting .................................................................... 308 22.18.2 Stop Mode.................................................................................................................................... 308 22.18.3 Wait Mode .............................................
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SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0000h 0040h 0041h CAN0 Wake-up Interrupt Control Register C01WKIC 61 0001h 0042h CAN0 Successful Reception Interrupt Control Register C0RECIC 61 0002h 0043h CAN0 Successful Transmission Interrupt Control Register C0TRMIC 61 0003h 0044h INT3 Interrupt Control Register INT3IC 62 0004h Processor Mode Register 0 PM0 28 Timer B5 Interrupt Control Register TB5IC 61 0005h Processor Mode Register 1 PM1 29 0045h SI/O5 Interrupt
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Address Register Symbol Page Address Register Symbol Page 0080h 00C0h 0081h 00C1h 0082h 00C2h CAN0 Message Box 2: Identifier / DLC CAN0 Message Box 6: Identifier / DLC 0083h 00C3h 0084h 00C4h 0085h 00C5h 0086h 00C6h 0087h 00C7h 0088h 00C8h 0089h 00C9h CAN0 Message Box 2: Data Field CAN0 Message Box 6: Data Field 008Ah 00CAh 008Bh 00CBh 008Ch 00CCh 008Dh 00CDh 008Eh 00CEh CAN0 Message Box 2: Time Stamp CAN0 Message Box 6: Time Stamp 008Fh 00CFh 0090h 00D0h 0091h 00D1h 0092h 00D2h CAN0 Message Box
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Address Register Symbol Page Address Register Symbol Page 0100h 0140h 0101h 0141h 0102h 0142h CAN0 Message Box 10: Identifier / DLC CAN0 Message Box 14: Identifier /DLC 0103h 0143h 0104h 0144h 0105h 0145h 0106h 0146h 0107h 0147h 0108h 0148h 0109h 0149h CAN0 Message Box 10: Data Field CAN0 Message Box 14: Data Field 010Ah 014Ah 010Bh 014Bh 010Ch 014Ch 010Dh 014Dh 010Eh 014Eh CAN0 Message Box 10: Time Stamp CAN0 Message Box 14: Time Stamp 010Fh 014Fh 200 0110h 0150h 201 0111h 0151h 0112h 0152h CAN
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Address Register Symbol Page Address Register Symbol Page 0180h 01C0h TBSR 107 Timer B3, B4, B5 Count Start Flag 0181h 01C1h 0182h 01C2h TA11 118 Timer A1-1 Register 0183h 01C3h 0184h 01C4h TA21 118 Timer A2-1 Register 0185h 01C5h 0186h 01C6h TA41 118 Timer A4-1 Register 0187h 01C7h 0188h 01C8h Three-Phase PWM Control Register 0 INVC0 115 0189h 01C9h Three-Phase PWM Control Register 1 INVC1 116 018Ah 01CAh Three-Phase Output Buffer Register 0 IDB0 117 018Bh 01CBh Three-Phase Output Buffer Regist
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Address Register Symbol Page Address Register Symbol Page 0200h 0240h CAN0 Message Control Register 0 C0MCTL0 0201h CAN0 Message Control Register 1 C0MCTL1 0241h 0202h CAN0 Message Control Register 2 C0MCTL2 0242h CAN0 Acceptance Filter Support Register C0AFS 209 0203h CAN0 Message Control Register 3 C0MCTL3 0243h 0204h CAN0 Message Control Register 4 C0MCTL4 0244h 0205h CAN0 Message Control Register 5 C0MCTL5 0245h 0206h CAN0 Message Control Register 6 C0MCTL6 0246h 0207h CAN0 Message Control R
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Address Register Symbol Page Address Register Symbol Page 0380h TABSR 92,107,120 03C0h Count Start Flag AD0 A/D Register 0 0381h Clock Prescaler Reset Flag CPSRF 93,107 03C1h 0382h One-Shot Start Flag ONSF 93 03C2h AD1 A/D Register 1 0383h Trigger Select Register TRGSR 93,120 03C3h 0384h Up/Down Flag UDF 92 03C4h AD2 A/D Register 2 0385h 03C5h 0386h 03C6h Timer A0 Register TA0 91 AD3 A/D Register 3 0387h 03C7h 180 0388h 91 03C8h Timer A1 Register AD4 TA1 A/D Register 4 0389h 118 03C9h 038Ah 91 0
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Under development This document is under development and its contents are subject to change M16C/6N Group (M16C/6NL, M16C/6NN) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.02 Jul 01, 2005 1. Overview The M16C/6N Group (M16C/6NL, M16C/6NN) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic molded LQFP. These single-chip microcomputers operate using sophisticated instructions f
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NL, M16C/6NN). Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NL) Item Performance CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait) Operation M
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NN) Item Performance CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait) Operation Mode Single-chip mode Address Space 1 Mbyte Memory Capacity See Table 1.3 Product List Peripheral Port Input/O
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8 7 8 8 Port P7 Port P8 Port P8_5 Port P9 Port P10 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN). 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Internal peripheral functions System clock generating circuit A/D converter (10 bits ✕ 8 channels XIN-XOUT XCIN-XCOUT Expandable up to 26 channels) P
