Summary of the content on the page No. 1
8086
16-BIT HMOS MICROPROCESSOR
8086/8086-2/8086-1
Y Y
Direct Addressing Capability 1 MByte Range of Clock Rates:
of Memory 5 MHz for 8086,
8 MHz for 8086-2,
Y
Architecture Designed for Powerful
10 MHz for 8086-1
Assembly Language and Efficient High
Y
Level Languages MULTIBUS System Compatible
Interface
Y
14 Word, by 16-Bit Register Set with
Y
Symmetrical Operations Available in EXPRESS
Ð Standard Temperature Range
Y
24 Operand Addressing Modes
Ð Extended Temperature Range
Y
Bit, Byte, Word, and
Summary of the content on the page No. 2
8086 Table 1. Pin Description The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ``Local Bus'' in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers). Symbol Pin No. Type Name and Function AD ±AD 2±16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed 15 0 memory/IO address (T ), and data (T ,T ,T ,T ) bus. A is 1 2 3 W 4 0 analogous to BHE for the lower by
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8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function READY 22 I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory/IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met. INTR 18 I INTERRUPT REQUEST: is a level triggered input whi
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8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function S ,S ,S 26±28 O These signals float to 3-state OFF in ``hold acknowledge''. These status 2 1 0 lines are encoded as shown. (Continued) S S S Characteristics 2 1 0 0 (LOW) 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1 (HIGH) 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive RQ/GT , 30, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to force 0 the proce
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8086 Table 1. Pin Description (Continued) Symbol Pin No. Type Name and Function QS ,QS 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after 1 0 which the queue operation is performed. QS and QS provide status to allow external tracking of the internal 1 0 8086 instruction queue. QS QS Characteristics 1 0 0 (LOW) 0 No Operation 0 1 First Byte of Op Code from Queue 1 (HIGH) 0 Empty the Queue 1 1 Subsequent Byte from Queue e The following pin function descriptions are for the
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8086 bytes, addressed as 00000(H) to FFFFF(H). The FUNCTIONAL DESCRIPTION memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries. General Operation (See Figure 3a.) The internal functions of the 8086 processor are partitioned logically into two processing units. The All memory references are made relative to base ad- first is the Bus Interface Unit (BIU) and the second is dresses contained in high speed
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8086 address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will al- ways begin execution at location FFFF0H where the jump must be. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset ad- dress. The pointer elements are assumed to h
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8086 231455±5 Figure 4a. Minimum Mode 8086 Typical Configuration 231455±6 Figure 4b. Maximum Mode 8086 Typical Configuration 8
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8086 can occur between 8086 bus cycles. These are re- S S S Characteristics 2 1 0 ferred to as ``Idle'' states (T) or inactive CLK cycles. i The processor uses these cycles for internal house- 0 (LOW) 0 0 Interrupt Acknowledge keeping. 0 0 1 Read I/O During T of any bus cycle the ALE (Address Latch 1 0 1 0 Write I/O Enable) signal is emitted (by either the processor or 0 1 1 Halt the 8288 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid ad- 1 (HIGH) 0 0
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8086 Status bits S through S are multiplexed with high- NMI asserted prior to the 2nd clock after the end of 3 7 order address bits and the BHE signal, and are RESET will not be honored. If NMI is asserted after therefore valid during T through T .S and S indi- that point and during the internal reset sequence, 2 4 3 4 cate which segment register (see Instruction Set de- the processor may execute one instruction before scription) was used for this bus cycle in forming the responding to the inter
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8086 MASKABLE INTERRUPT (INTR) HALT The 8086 provides a single interrupt request input When a software ``HALT'' instruction is executed the (INTR) which can be masked internally by software processor indicates that it is entering the ``HALT'' with the resetting of the interrupt enable FLAG state in one of two ways depending upon which status bit. The interrupt request signal is level trig- mode is strapped. In minimum mode, the processor gered. It is internally synchronized during each clock iss
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8086 EXTERNAL SYNCHRONIZATION VIA TEST SYSTEM TIMINGÐMINIMUM SYSTEM As an alternative to the interrupts and general I/O The read cycle begins in T with the assertion of the 1 capabilities, the 8086 provides a single software- Address Latch Enable (ALE) signal. The trailing (low- testable input known as the TEST signal. At any time going) edge of this signal is used to latch the ad- the program may execute a WAIT instruction. If at dress information, which is valid on the local bus at that time t
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8086 lines D ±D as supplied by the inerrupt system logic acknowledge, or software halt. The 8288 thus issues 7 0 (i.e., 8259A Priority Interrupt Controller). This byte control signals specifying memory read or write, I/O identifies the source (type) of the interrupt. It is multi- read or write, or interrupt acknowledge. The 8288 plied by four and used as a pointer into an interrupt provides two types of write strobes, normal and ad- vector lookup table, as described earlier. vanced, to be applie
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8086 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. Ambient Temperature Under Bias ÀÀÀÀÀÀ0 Cto70 C § § *WARNING: Stressing the device beyond the ``Absolute b a Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 Cto 150 C § § Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the Voltage on Any Pin with ``Operating Conditions'' is not recommended and ex- b a Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1.0
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8086 e e A.C. CHARACTERISTICS (8086: T 0 Cto70 C, V 5V g 10%) § § A CC e e (8086-1: T 0 Cto70 C, V 5V g 5%) § § A CC e e (8086-2: T 0 Cto70 C, V 5V g 5%) § § A CC MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS 8086 8086-1 8086-2 Symbol Parameter Units Test Conditions Min Max Min Max Min Max TCLCL CLK Cycle Period 200 500 100 500 125 500 ns TCLCH CLK Low Time 118 53 68 ns TCHCL CLK High Time 69 39 44 ns TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V
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8086 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES 8086 8086-1 8086-2 Test Symbol Parameter Units Conditions Min Max Min Max Min Max TCLAV Address Valid Delay 10 110 10 50 10 60 ns TCLAX Address Hold Time 10 10 10 ns TCLAZ Address Float TCLAX 80 10 40 TCLAX 50 ns Delay TLHLL ALE Width TCLCH-20 TCLCH-10 TCLCH-10 ns TCLLH ALE Active Delay 80 40 50 ns TCHLL ALE Inactive Delay 85 45 55 ns TLLAX Address Hold Time TCHCL-10 TCHCL-10 TCHCL-10 ns e TCLDV Data Valid Delay 10 110 10 50 10 60 ns *C 20±1
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8086 A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 231455-11 A.C. Testing: Inputs are driven at 2.4V for a Logic ``1'' and 0.45V 231455±12 for a Logic ``0''. Timing measurements are made at 1.5V for both a Logic ``1'' and ``0''. C Includes Jig Capacitance L WAVEFORMS MINIMUM MODE 231455±13 17
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8086 WAVEFORMS (Continued) MINIMUM MODE (Continued) 231455±14 SOFTWARE HALTÐ RD, WR, INTA e V OH DT/R e INDETERMINATE NOTES: 1. All signals switch between V and V unless otherwise specified. OH OL 2. RDY is sampled near the end of T ,T ,T to determine if T machines states are to be inserted. 2 3 W W 3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control signals shown for second INTA cycle. 4. Signals at 8284A are shown for reference only. 5
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8086 A.C. CHARACTERISTICS MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS 8086 8086-1 8086-2 Test Symbol Parameter Units Conditions Min Max Min Max Min Max TCLCL CLK Cycle Period 200 500 100 500 125 500 ns TCLCH CLK Low Time 118 53 68 ns TCHCL CLK High Time 69 39 44 ns TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V to 1.0V TDVCL Data in Setup Time 30 5 20 ns TCLDX Data in Hold Time 10 10 10 ns TR1VCL RDY Setup Time 35 35 35 ns into
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8086 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES 8086 8086-1 8086-2 Test Symbol Parameter Units Conditions Min Max Min Max Min Max TCLML Command Active 10 35 10 35 10 35 ns Delay (See Note 1) TCLMH Command Inactive 10 35 10 35 10 35 ns Delay (See Note 1) TRYHSH READY Active to 110 45 65 ns Status Passive (See Note 3) TCHSV Status Active Delay 10 110 10 45 10 60 ns TCLSH Status Inactive 10 130 10 55 10 70 ns Delay TCLAV Address Valid Delay 10 110 10 50 10 60 ns TCLAX Address Hold Time 10 10
