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MC68HC08KH12
Data Sheet
M68HC08
Microcontrollers
Rev. 1.1
MC68HC08KH12/H
July 15, 2005
freescale.com
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Advance Information — MC68HC(7)08KH12 List of Sections Section 1. General Description .......................................23 Section 2. Memory Map ...................................................33 Section 3. Random-Access Memory (RAM) ...................45 Section 4. Read-Only Memory (ROM) .............................47 Section 5. Configuration Register (CONFIG) .................49 Section 6. Central Processor Unit (CPU) .......................51 Section 7. System Integration Module (SIM
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Advance Information MC68HC(7)08KH12 — Rev. 1.1 4 Freescale Semiconductor
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Advance Information — MC68HC(7)08KH12 Table of Contents General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5 Pin Assignments. . . . . . . . . .
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2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Section 3. Random-Access Memory (RAM) 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . .
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Section 7. System Integration Module (SIM) 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .65 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.3.
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7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . .84 7.8.3 Break Flag Control Register (BFCR). . . . . . . . . . . . . . . . . .85 Section 8. Clock Generator Module (CGM) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 8.4
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8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.8.2 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .108 8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .108 8.9.1 Acquisition/Lock Time Definitions . . . . . .
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9.5.7 USB Embedded Device Control Register 2 (DCR2) . . . . .146 9.5.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 9.5.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Section 10. Monitor ROM (MON) 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.2 Introduction. . . . . . . . . . . . . . .
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11.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.8.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .172 11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1). . . . . . .173 11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . .
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12.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .202 12.8.2 Data Direction Register F (DDRF). . . . . . . . . . . . . . . . . . .203 12.9 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.9.1 Port Option Control Register (POC) . . . . . . . . . . . . . . . . .204 Section 13. Computer Operating Properly (COP) 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.2 Introduct
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14.4.1 IRQ1/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 PP 14.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .217 14.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .217 Section 15. Keyboard Interrupt Module (KBI) 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 15.3
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Section 16. Break Module (BREAK) 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . .244 16
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17.12 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . . .255 17.13 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 17.14 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . .256 17.15 Clock Generation Module Characteristics . . . . . . . . . . . . . . .257 17.15.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .257 17.15.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .257 1
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Advance Information MC68HC(7)08KH12 — Rev. 1.1 16 Freescale Semiconductor
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Advance Information — MC68HC(7)08KH12 List of Figures Figure Title Page 1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1-2 64-Pin QFP Assignments (Top View). . . . . . . . . . . . . . . . . . . .28 1-3 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . .
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Figure Title Page 7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 7-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .81 7-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .81 7-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . . .82 7-20 Break Status Register (BSR) . . . . . . . . . . . . .
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Figure Title Page 9-20 USB Embedded Device Endpoint 0 Data Register (UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 10-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .154 10-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure Title Page 12-20 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .203 12-21 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 12-22 Port Option Control Register (POC) . . . . . . . . . . . . . . . . . . . .204 13-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 13-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .210 13-3 COP Control Register (COPCTL). . . . .
