Summary of the content on the page No. 3
Z9973 inputs (see Table 1). The VCO frequency is then divided to Functional Description provide the required output frequencies. These dividers are The Z9973 has an integrated PLL that provides low-skew and set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see low-jitter clock outputs for high-performance microprocessors. Table 2). For situations in which the VCO needs to run at Three independent banks of four outputs as well as an relatively low frequencies and hence might not be stable,
Summary of the content on the page No. 4
Z9973 VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC Figure 1. Sync Output Waveforms Document #: 38-07089 Rev. *D Page 4 of 9 [+] Feedback
Summary of the content on the page No. 5
Z9973 serial data. An output is frozen when a logic “0” is programmed Power Management and enabled when a logic “1” is written. The enabling and The individual output enable/freeze control of the Z9973 freezing of individual outputs is done in such a manner as to allows the user to implement unique power management eliminate the possibility of partial “runt” clocks. schemes into the design. The outputs are stopped in the logic The serial input register is programmed through the SDATA “0” stat
Summary of the content on the page No. 6
Z9973 [3] Maximum Ratings Maximum Input Voltage Relative to V : ............ V – 0.3V This device contains circuitry to protect the inputs against SS SS damage due to high static voltages or electric field; however, Maximum Input Voltage Relative to V :............. V + 0.3V DD DD precautions should be taken to avoid application of any Storage Temperature: ................................–65°C to + 150°C voltage higher than the maximum rated voltages to this circuit. For proper operation, V an
Summary of the content on the page No. 7
Z9973 [4] AC Parameters (V = 2.9V to 3.6V, V = 3.3V ±10%, T = –40°C to +85°C) (Continued) DD DDC A Parameter Description Conditions Min. Typ. Max. Units Fout Maximum Output Frequency Q (÷2) 125 MHz Q (÷4) 120 Q (÷6) 80 Q (÷8) 60 [6] FoutDC Output Duty Cycle TCYCLE TCYCLE ps /2 – 750 /2 + 750 [6] tpZL, tpZH Output Enable Time (all outputs) 2 10 ns [6] tpLZ, tpHZ Output Disable Time (all outputs) 2 8 ns [6] TCCJ Cycle to Cycle Jitter (peak to peak) ± 100 ps [6,7] TSKEW Any Output to Any Output
Summary of the content on the page No. 8
Z9973 Package Drawing and Dimensions 52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52 51-85131-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07089 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypres
Summary of the content on the page No. 9
Z9973 Document Title: Z9973 3.3V, 125 MHz Multi-Output Zero Delay Buffer Document Number: 38-07089 Orig. of Rev. ECN No. Issue Date Change Description of Change ** 107125 06/06/01 IKA Convert from IMI to Cypress *A 108067 07/03/01 NDP Changed Commercial to Industrial *B 111799 02/06/02 BRK Convert from Word Doc to Adobe Framemaker Cypress Format Changed the Timing Diagram and the operating voltage condition *C 116452 07/30/02 HWT Corrected the Ordering Information to match the DevMaster. *D 1
Summary of the content on the page No. 1
SELB1 FB_SEL1
SELB0 SYNC
SELA1 VSS
SELA0 QC0
QA3 VDDC
VDDC QC1
QA2 SELC0
VSS SELC1
QA1 QC2
VDDC VDDC
QA0 QC3
VSS VSS
VCO_SEL INV_CLK
Z9973
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
[1]
Features
Table 1. Frequency Table
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 F
VC0
• Output frequency up to 125 MHz
0000 8x
12 clock outputs: frequency configurable
0001 12x
350 ps max output-to-output skew
0010 16x
Configurable output disable
0011 20x
Two reference clock inputs for dynamic toggling
0100 16x
Summary of the content on the page No. 2
Z9973 [2] Pin Description Pin Number Pin Name PWR I/O Type Pin Description 11 PECL_CLK I PU PECL Clock Input. 12 PECL_CLK# I PD PECL Clock Input. 9TCLK0 IPU External Reference/Test Clock Input. 10 TCLK1 I PU External Reference/Test Clock Input. 44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 29
