Summary of the content on the page No. 1
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
FLEx36™ 3.3V 32K/64K/128K/256K x 36
Synchronous Dual-Port RAM
Features Functional Description
■ True dual-ported memory cells that allow simultaneous access
The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,
of the same memory location
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3V CMOS. Two ports are provided, permitting
■ Synchronous pipelined operation
independent, simultaneous access to any location in memor
Summary of the content on the page No. 2
CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [1] Logic Block Diagram OE OE L R R/W R/W L R B0 B0 L R B1 B1 L R B2 B2 L R B3 B3 L R CE CE 0L 0R CE CE 1L 1R 9 9 DQ –DQ DQ –DQ 27L 35L 27R 35R 9 9 DQ –DQ DQ –DQ 18L 26L 18R 26R I/O I/O 9 9 DQ –DQ Control Control DQ –DQ 9L 17L 9R 17R 9 9 DQ –DQ DQ –DQ 0L 8L 0R 8R Addr. Addr. Read Read True Back Back Dual-Ported RAM Array 18 18 A –A A –A 0L 17L 0R 17R Mask Register Mask Register CNT/MSK CNT/MSK R L ADS ADS Counter/ Counter/ L Address Address A
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Pin Configurations Figure 1. 172-Ball BGA (Top View) 1 2 3 456789 10 11 12 13 14 DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R A A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R B C NC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R D A4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R E F VDD A
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Pin Configurations (continued) Figure 2. 172-Ball BGA (Top View) 1 23456 789 10 11 12 13 14 DQ32L DQ30L NC VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS NC DQ30R DQ32R A A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R B C A17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R D A4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R E F
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Pin Configurations (continued) Figure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View) DQ 132 34R 1 DQ 34L DQ 131 35R 2 DQ 35L NC 130 NC 3 A 129 0R A 4 0L A 128 1R 5 A 1L A 127 2R 6 A 2L A 126 7 3R A 3L V 125 SS 8 V SS V 124 DD V 9 DD A 123 4R 10 A 4L A 122 5R A 11 5L A 121 6R 12 A 6L A 120 7R 13 A 7L B 119 0R B 14 0L B 118 1R 15 B 1L CE 117 1R 16 CE 1L B 116 2R B 17 2L B 115 3R 18 B 3L OE 114 R 19 OE L CE 113 0R CE 20 CY7C0850AV 0L V 112 DD 21 V
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Pin Definitions Left Port Right Port Description [1] [1] A –A A –A Address Inputs. 0L 17L 0R 17R [3] [3] ADS ADS Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for L R the part using the externally supplied address on the address pins and for loading this address into the burst address counter. [3] [3] CE0 CE0 Active LOW Chip Enable Input. L R [3] [3] CE1 CE1 Active HIGH Chip Enable Input. L R CLK Clock Si
Summary of the content on the page No. 7
CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV in order to set the INT flag, a Write operation by the left port to Master Reset R address 3FFFF asserts INT LOW. At least one byte has to be R active for a Write to generate an interrupt. A valid Read of the The FLEx36 family devices undergo a complete reset by taking 3FFFF location by the right port resets INT HIGH. At least one its MRST input LOW. The MRST input can switch asynchro- R byte has to be active in order for a Read to reset the inte
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV will reset the counter and mirror registers to 00000, as will master Address Counter and Mask Register reset (MRST). Operations Counter Load Operation [10] This section describes the features only apply to The address counter and mirror registers are both loaded with CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not to the address value presented at the address lines. the CY7C0853AV device. Each port of these devices has a programmable burst addre
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Counter Interrupt Mask Load Operation The counter interrupt (CNTINT) is asserted LOW when an The mask register is loaded with the address value presented at increment operation results in the unmasked portion of the the address lines. Not all values permit correct increment opera- n n counter register being all “1s.” It is deasserted HIGH when an tions. Permitted values are of the form 2 – 1 or 2 – 2. From the Increment operation results in any ot
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [1] Figure 4. Counter, Mask, and Mirror Logic Block Diagram CNT/MSK CNTEN Decode ADS Logic CNTRST MRST Bidirectional Mask Address Register Lines Counter/ Address RAM Address Decode Array Register CLK Load/Increment From 17 Address Mirror Counter Lines To Readback 1 1 and Address 0 Decode 0 From 17 Increment Mask Logic 17 Wrap Register 17 17 From Mask Bit 0 17 From +1 Wrap Counter Wrap 1 Detect 0 +2 17 1 To Counter 0 Document #: 38-06070 R
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [1, 12] Figure 5. Programmable Counter-Mask Register Operation CNTINT Example: Load Counter-Mask H 0 0 0s01 11 1 1 1 Register = 3F 16 15 6 5 4 3 2 1 0 Mask 2 2 2 2 2 2 2 2 2 Register Masked Address Unmasked Address bit-0 Load Address H X X Xs X0 00 1 0 0 Counter = 8 16 15 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 Address Counter Max bit-0 Address L X X Xs X1 11 1 1 1 Register 16 15 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 Max + 1 Address H X X XsX0 00 1 0 0 Register
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [13] Performing a TAP Reset IEEE 1149.1 Serial Boundary Scan (JTAG) A reset is performed by forcing TMS HIGH (V ) for five rising DD The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV edges of TCK. This reset does not affect the operation of the incorporates an IEEE 1149.1 serial boundary scan test access devices, and may be performed while the devices are operating. port (TAP). The TAP controller functions in a manner that does An MRST must be perfo
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [16] DC Input Voltage .............................. –0.5V to V + 0.5V Maximum Ratings DD Output Current into Outputs (LOW)............................. 20 mA [15] Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage........................................... > 2000V device. These user guidelines are not tested. (JEDEC JESD22-A114-2000B) °C to + 150 °C Storage Temperature................................ –65 Latch-up
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Figure 6. AC Test Load and Waveforms 3.3V Z = 50 Ω R = 50 Ω 0 OUTPUT R1 = 590 Ω OUTPUT C = 10 pF C = 5 pF V = 1.5V R2 = 435 Ω TH (a) Normal Load (Load 1) (b) Three-state Delay (Load 2) 3.0V 90% 90% 10% 10% ALL INPUT PULSES V SS <2ns <2ns Switching Characteristics Over the Operating Range -167 -133 -100 CY7C0850AV CY7C0850AV Parameter Description CY7C0851AV CY7C0851AV CY7C0853AV CY7C0853AV Unit CY7C0852AV CY7C0852AV Min Max Min Max Min Max Min Ma
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Switching Characteristics Over the Operating Range (continued) -167 -133 -100 CY7C0850AV CY7C0850AV Parameter Description CY7C0851AV CY7C0851AV CY7C0853AV CY7C0853AV Unit CY7C0852AV CY7C0852AV Min Max Min Max Min Max Min Max t Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns OE [20, 21] t OE to Low Z 0 0 0 0 ns OLZ [20, 21] t OE to High Z 0 4.00 4.404.7 05.0 ns OHZ t Clock to Data Valid 4.0 4.4 4.7 5.0 ns CD2 t Clock to Counter Address Valid 4.0 4.
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV JTAG Timing 167/133/100 Parameter Description Unit Min Max f Maximum JTAG TAP Controller Frequency 10 MHz JTAG t TCK Clock Cycle Time 100 ns TCYC t TCK Clock HIGH Time 40 ns TH t TCK Clock LOW Time 40 ns TL t TMS Setup to TCK Clock Rise 10 ns TMSS t TMS Hold After TCK Clock Rise 10 ns TMSH t TDI Setup to TCK Clock Rise 10 ns TDIS t TDI Hold After TCK Clock Rise 10 ns TDIH t TCK Clock LOW to TDO Valid 30 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Switching Waveforms Figure 8. Master Reset t RS MRST t ALL RSF ADDRESS/ DATA t LINES RSS t RSR ALL INACTIVE OTHER ACTIVE INPUTS TMS CNTINT INT TDO [4, 22, 23, 24, 25] Figure 9. Read Cycle t CYC2 t t CH2 CL2 CLK CE t t t t SC HC SC HC t SB t HB B0–B3 R/W t t SW HW t t SA HA ADDRESS A A A A n n+1 n+2 n+3 t 1 Latency t DC CD2 DATA OUT Q Q Q n n+1 n+2 t OHZ t t CKLZ OLZ OE t OE Notes 22. OE is asynchronously controlled; all other inputs (excluding
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Switching Waveforms (continued) [26, 27] Figure 10. Bank Select Read t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A A A A A (B1) 0 A 3 4 5 1 2 t t HC SC CE (B1) t t t t t t CD2 t CD2 CD2 CKHZ HC CKHZ SC Q Q Q 3 DATA 0 1 OUT(B1) t t HA SA t t t DC DC CKLZ ADDRESS A A A A A A (B2) 0 3 4 5 1 2 t t SC HC CE (B2) t t t t CD2 CKHZ CD2 t SC HC DATA OUT(B2) Q Q 4 2 t t CKLZ CKLZ [25, 28, 29, 30, 31] Figure 11. Read-to-Write-to-Read (OE = LOW) t CYC2 t t CH
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Switching Waveforms (continued) [25, 28, 30, 31] Figure 12. Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK CE t t SC HC t t SW HW R/W t t SW HW A A A A A A n n+1 n+2 n+3 n+4 n+5 ADDRESS t t t t SA HA SD HD D DATA D n+2 IN n+3 t t CD2 t CD2 CD2 DATA OUT Q Q Q n n+1 n+4 t OHZ OE READ WRITE READ [30] Figure 13. Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A n t t SAD HAD ADS t t SAD HAD CNTEN t t SCN HC
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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Switching Waveforms (continued) [31] Figure 14. Write with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA A ADDRESS n INTERNAL A A A A A n n+1 n+2 n+3 n+4 ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D D D D D D DATA n n+1 n+1 n+2 n+3 n+4 IN t t SD HD WRITE EXTERNAL WRITE WITH WRITE COUNTER WRITE WITH COUNTER ADDRESS COUNTER HOLD Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write t CYC2 t t CL2 CH2 CLK t t SC HC CE t t SW HW R/W t t SW
