Summary of the content on the page No. 1
CY7C1370D
CY7C1372D
18-Mbit (512K x 36/1M x 18) Pipelined
SRAM with NoBL™ Architecture
Features Functional Description
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and
• Pin-compatible and functionally equivalent to ZBT™
1M x 18 Synchronous pipelined burst SRAMs with No Bus
• Supports 250-MHz bus operations with zero wait states
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
— Available speed grades are 250, 200 and 167
Summary of the content on the page No. 2
CY7C1370D CY7C1372D Logic Block Diagram-CY7C1372D (1M x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U A ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BWa WRITE E DQs U ARRAY S CONTROL LOGIC G DRIVERS A F T DQPa I M F E BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Selecti
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CY7C1370D CY7C1372D Pin Configurations 100-pin TQFP Pinout DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V 4 V DDQ 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 71 SS V V DDQ DDQ 11 V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS CY7C1370D 67 SS V V DD 15 NC DD 15 NC 66 CY7C1372
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CY7C1370D CY7C1372D Pin Configurations (continued) 119-Ball BGA Pinout CY7C1370D (512K x 36) 1 23 4 5 6 7 A V AAAV A A DDQ DDQ B NC/576M CE A ADV/LD ACE NC 2 3 C NC/1G A A V AA NC DD D DQ DQP V NC V DQP DQ c c SS SS b b DQ DQ V CE V DQ DQ E c c SS 1 SS b b F V DQ V V DQ V OE DDQ c SS SS b DDQ DQ DQ A DQ DQ G BW BW c c b b c b DQ DQ V DQ DQ H V c c SS WE b b SS V V NC V NC V V J DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ d d SS SS a a L DQ DQ NC DQ DQ BW BW d d a a d a M V DQ V V DQ V CEN DDQ d S
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CY7C1370D CY7C1372D Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1370D (512K x 36) 1 234 5 6 7 89 10 11 A NC/576M A ADV/LD A A NC CE BW BW CE CEN 1 c b 3 B NC/1G A CE2 CLK WE OE A A NC BW BW d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS SS SS DDQ b DQ DQ V V V V V V V DQ DQ D c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ E c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ G c c DDQ DD SS SS SS DD DDQ
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CY7C1370D CY7C1372D Pin Definitions Pin Name I/O Type Pin Description A0 Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of A1 Synchronous the CLK. A BW Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. a BW Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , b a a a b b b BW BW controls DQ and DQP , BW controls DQ and DQP . c c c c d d d BW d WE Input- Writ
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CY7C1370D CY7C1372D Pin Definitions (continued) Pin Name I/O Type Pin Description V I/O Power Power supply for the I/O circuitry. DDQ Supply V Ground Ground for the device. Should be connected to ground of the system. SS NC – No connects. This pin is not connected to the die. NC/(36M,72M, – These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 144M, 288M, 576M and 1G densities. 576M, 1G) ZZ Input- ZZ “sleep” Input. This active HIGH input places the device
Summary of the content on the page No. 8
CY7C1370D CY7C1372D Asserting the Write Enable input (WE) with the selected Byte Sleep Mode Write Select (BW) input will selectively write to only the desired The ZZ input pin is an asynchronous input. Asserting ZZ bytes. Bytes not selected during a byte write operation will places the SRAM in a power conservation “sleep” mode. Two remain unaltered. A synchronous self-timed write mechanism clock cycles are required to enter into or exit from this “sleep” has been provided to simplify the write
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CY7C1370D CY7C1372D [1, 2, 3, 4, 5, 6, 7] Truth Table Address Operation Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State Write Cycle (Begin Burst
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CY7C1370D CY7C1372D [1, 2, 3, 8] Partial Write Cycle Description Function (CY7C1370D) WE BW BW BW BW d c b a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ and DQP) L HHH L a a Write Byte b – (DQ and DQP)LHHLH b b Write Bytes b, a L H H L L Write Byte c – (DQ and DQP)LHLHH c c Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQ and DQP)LLHHH d d Write Bytes d, a L L H H L Write Bytes d, b L LHLH Write Bytes d, b, a L L
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CY7C1370D CY7C1372D Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the The CY7C1370D/CY7C1372D incorporates a serial boundary registers and can be connected to the input of any of the scan test access port (TAP). This part is fully compliant with registers. The register between TDI and TDO is chosen by the 1149.1. The TAP operates using JEDEC-standard 3.3V or instruction that is loaded into the TAP instruction register. TDI 2.
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CY7C1370D CY7C1372D When the TAP controller is in the Capture-IR state, the two the IDCODE to be shifted out of the device when the TAP least significant bits are loaded with a binary “01” pattern to controller enters the Shift-DR state. allow for fault isolation of the board-level serial test data path. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test Bypass Register logic reset state. To save time when serially shifti
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CY7C1370D CY7C1372D in the TAP controller, it will directly control the state of the register. When the EXTEST instruction is entered, this bit will output (Q-bus) pins, when the EXTEST is entered as the directly control the output Q-bus pins. Note that this bit is current instruction. When HIGH, it will enable the output preset HIGH to enable the output when the device is buffers to drive the output bus. When LOW, this bit will place powered-up, and also when the TAP controller is in the the
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CY7C1370D CY7C1372D 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Input timing refere
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CY7C1370D CY7C1372D Identification Register Definitions Instruction Field CY7C1372D CY7C1370D Description Revision Number (31:29) 000 000 Reserved for version number. [12] Cypress Device ID (28:12) 01011001000100101 01011001000010101 Reserved for future use. Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (x18) Bit Size (x36) Instruction
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CY7C1370D CY7C1372D [13, 14] 119-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 23 F6 45 G4 67 L1 H4 2T4 24 E7 46 A4 68 M2 3T5 25 D7 47 G3 69 N1 4T6 26 H7 48 C3 70 P1 5R5 27 G6 49 B2 71 K1 6L5 28 E6 50 B3 72L2 7R6 29 D6 51 A3 73 N2 8U6 30 C7 52 C2 74 P2 9R7 31 B7 53 A2 75R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61
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CY7C1370D CY7C1372D [13, 15] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N6 31 D10 61 G1 2N7 32 C11 62 D2 3N10 33 A11 63 E2 4P11 34 B11 64 F2 5P8 35 A10 65 G2 6R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2
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CY7C1370D CY7C1372D Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied...............
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CY7C1370D CY7C1372D [18] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 589 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 8 9 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 8 9 pF I/O [18] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 28.66 23.8 20.7 °C/W JA (Junction to Ambient) te
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CY7C1370D CY7C1372D [23, 24] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max. Min. Max. Min. Max. Unit [19] t V (typical) to the first access read or write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5 6 ns CYC F Maximum Operating Frequency 250 200 167 MHz MAX t Clock HIGH 1.7 2.0 2.2 ns CH t Clock LOW 1.7 2.0 2.2 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.0 3.4 ns CO t OE LOW to Output Valid 2.6 3.0 3.4 ns EOV t Data Output
