Summary of the content on the page No. 1
CY7C1355C
CY7C1357C
9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM with NoBL™ Architecture
[1]
Features Functional Description
• No Bus Latency™ (NoBL™) architecture eliminates The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18
dead cycles between write and read cycles Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
• Can support up to 133-MHz bus operations with zero
without the insertion of wait states. The
wait st
Summary of the content on the page No. 2
CY7C1355C CY7C1357C 1 Logic Block Diagram – CY7C1355C (256K x 36) ADDRESS A0, A1, A A1 REGISTER A1' D1 Q1 A0 A0' D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T N ADV/LD A S B MEMORY BWA WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BWB AND DATA COHERENCY T DQPA A F E CONTROL LOGIC DQPB BWC M E E DQPC P R R BWD DQPD S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1357C (512K x 18) ADDRESS A0, A1,
Summary of the content on the page No. 3
CY7C1355C CY7C1357C Pin Configurations 100-Pin TQFP Pinout DQP 80 C 1 DQP B DQ 79 2 C DQ B DQ 78 C 3 DQ B V 77 4 DDQ V DDQ V 76 SS 5 V SS DQ 75 6 DQ C B BYTE C BYTE B DQ 74 C 7 DQ B DQ 73 8 C DQ B DQ 72 C 9 DQ B V 71 10 V SS SS V 70 DDQ 11 V DDQ DQ 69 12 DQ C B DQ 68 13 C DQ B CY7C1355C Vss/DNU 67 14 V SS V 66 15 DD NC NC 65 16 V DD V 64 17 ZZ SS DQ 63 18 DQ D A DQ 62 19 D DQ A V 61 20 V DDQ DDQ V 60 21 SS V SS DQ 59 22 DQ D A DQ 58 23 D DQ BYTE D A BYTE A DQ 57 24 DQ D A DQ 56 25 DQ D A V
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CY7C1355C CY7C1357C Pin Configurations (continued) 100-Pin TQFP Pinout NC 80 1 A NC 79 2 NC NC 78 3 NC V 77 4 DDQ V DDQ V 76 SS 5 V SS NC 75 6 NC NC 74 7 DQP A DQ 73 8 DQ B A DQ 72 9 B DQ A V 71 10 V SS SS V 70 11 DDQ V DDQ DQ 69 12 DQ B A DQ 68 13 B DQ A CY7C1357C Vss/DNU 67 14 V SS BYTE A V 66 15 DD NC BYTE B NC 65 16 V DD V 64 ZZ 17 SS DQ 63 18 DQ B A DQ 62 19 B DQ A V 61 DDQ 20 V DDQ V 60 21 SS V SS DQ 59 B 22 DQ A DQ 58 23 B DQ A DQP 57 B 24 NC NC 56 25 NC V 55 SS 26 V SS V 54 27 V DDQ
Summary of the content on the page No. 5
CY7C1355C CY7C1357C Pin Configurations (continued) 119-Ball BGA Pinout (3 Chip Enables with JTAG) CY7C1355C (256K x 36) 1 23 4 5 6 7 A V AA NC/18M A A V DDQ DDQ B NC/576M CE A ADV/LD A CE NC 2 3 C NC/1G A A V A A NC DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V V DQ DQ CE C C SS SS B B 1 F V DQ V V DQ V DDQ C SS OE SS B DDQ G DQ DQ A DQ DQ BW BW C C B B C B H DQ DQ V V DQ DQ WE C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D
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CY7C1355C CY7C1357C Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip enable with JTAG) CY7C1355C (256K x 36) 1 234 5 6 7 89 10 11 NC/576M CE BW BW CE CEN ADV/LD A A NC A A 1 C B 3 NC/1G A CE2 BW BW CLK WE OE NC/18M A NC B D A C DQP NC V V V V V V V NC DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ DQ V V V V V V V DQ D
Summary of the content on the page No. 7
CY7C1355C CY7C1357C Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the address locations. Sampled at the rising edge 0 1 Synchronous of the CLK. A are fed to the two-bit burst counter. [1:0] BW , BW Input- Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled A B BW , BW Synchronous on the rising edge of CLK. C D WE Input- Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. Syn
Summary of the content on the page No. 8
CY7C1355C CY7C1357C Pin Definitions (continued) Name I/O Description TMS JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to V . This pin is not DD available on TQFP packages. TCK JTAG Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must Clock be connected to V . This pin is not available on TQFP packages. SS NC – No
Summary of the content on the page No. 9
CY7C1355C CY7C1357C precaution, DQs and DQP are automatically tri-stated during Interleaved Burst Address Table X the data portion of a write cycle, regardless of the state of OE. (MODE = Floating or VDD) Burst Write Accesses First Second Third Fourth Address Address Address Address The CY7C1355C/CY7C1357C has an on-chip burst counter A1: A0 A1: A0 A1: A0 A1: A0 that allows the user the ability to supply a single address and 00 01 10 11 conduct up to four Write operations without reasserti
Summary of the content on the page No. 10
CY7C1355C CY7C1357C [2, 3, 4, 5, 6, 7, 8] Truth Table Address Operation Used CE CE CE ZZ ADV/LD WE BW OE CEN CLK DQ 1 2 3 X NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-State WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H – SLEEP MODE None X X X H X X X X X X Tri-State [2, 3, 9] Partial Truth Table for Read/Write Function (CY7C1355C) WE BW BW BW BW A B C D Read H X X X X Write No bytes written L H H
Summary of the content on the page No. 11
CY7C1355C CY7C1357C Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1355C/CY7C1357C incorporates a serial boundary and is sampled on the rising edge of TCK. It is allowable to scan test access port (TAP) in the BGA package only. The leave this ball unconnected if the TAP is not used. The ball is TQFP package does not offer this functionality. This part pulled up internally, resulting in a logic HIGH level. oper
Summary of the content on the page No. 12
CY7C1355C CY7C1357C Diagram. Upon power-up, the instruction register is loaded SAMPLE Z with the IDCODE instruction. It is also loaded with the IDCODE The SAMPLE Z instruction causes the boundary scan register instruction if the controller is placed in a reset state as to be connected between the TDI and TDO pins when the TAP described in the previous section. controller is in a Shift-DR state. The SAMPLE Z command puts When the TAP controller is in the Capture-IR state, the two the output bus
Summary of the content on the page No. 13
CY7C1355C CY7C1357C TAP Timing 123456 Test Clock (TCK) t t t TH TL CYC t t TMSS TMSH Test Mode Select (TMS) t t TDIS TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED [10, 11] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH Time 20 ns TH t TCK Clock LOW Time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock
Summary of the content on the page No. 14
CY7C1355C CY7C1357C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Input timing refer
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CY7C1355C CY7C1357C Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. IDCODE 001 Loads the ID register with the vendor ID
Summary of the content on the page No. 16
CY7C1355C CY7C1357C 119-ball BGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Signal Signal Signal Signal Bit# ball ID Name Bit# ball ID Name Bit# ball Id Name Bit# ball Id Name 1 CLK 37 R6 A 1 CLK 37 R6 A K4 K4 2H4 WE 38 T5 A 2 H4 WE 38 T5 A 3M4 CEN 39 T3 A 3 M4 CEN 39 T3 A 4F4 OE 40 R2 A 4 F4 OE 40 R2 A 5B4 ADV/LD 41 R3 MODE 5 B4 ADV/LD 41 R3 MODE 6G4 A 42 P2 DQP 6 G4 A 42 Internal Internal D 7C3 A 43 P1 DQ 7 C3 A 43 Internal Internal D 8 B3 A 44 L2 DQ 8 B3 A 44 Internal
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CY7C1355C CY7C1357C 165-ball FBGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Signal Signal Signal Signal Bit# ball ID Name Bit# ball ID Name Bit# ball ID Name Bit# ball ID Name 1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A 2B7 WE 38 P4 A 2 B7 WE 38 P4 A 3A7 CEN 39 R3 A 3 A7 CEN 39 R3 A 4B8 OE 40 P3 A 4 B8 OE 40 P3 A 5A8 ADV/LD 41 R1 MODE 5 A8 ADV/LD 41 R1 MODE 6 A9 A 42 N1 DQP 6 A9 A 42 Internal Internal D 7B10 A 43 L2 DQ 7 B10 A 43 Internal Internal D 8A10 A 44 K2 DQ 8 A10 A 44 Int
Summary of the content on the page No. 18
CY7C1355C CY7C1357C DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current........................................
Summary of the content on the page No. 19
CY7C1355C CY7C1357C [15] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 55 5 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 5 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 7 7 pF I/O [15] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 29.41 34.1 16.8 °C/W JA (Junction to Ambient) t
Summary of the content on the page No. 20
CY7C1355C CY7C1357C [16, 17] Switching Characteristics Over the Operating Range –133 –100 Parameter Description Min. Max. Min. Max. Unit [18] t V (Typical) to the First Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 3.0 4.0 ns CH t Clock LOW 3.0 4.0 ns CL Output Times t Data Output Valid after CLK Rise 6.5 7.5 ns CDV t Data Output Hold after CLK Rise 2.0 2.0 ns DOH [19, 20, 21] t Clock to Low-Z 00 ns CLZ [19, 20, 21] t Clock to High-Z 3.5 3.5 ns CHZ t OE LOW to Outpu
