Summary of the content on the page No. 1
®
CY62138F MoBL
2-Mbit (256K x 8) Static RAM
[1]
Features Functional Description
• High speed: 45 ns The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
• Wide voltage range: 4.5 V – 5.5 V
advanced circuit design to provide ultra low active current.
• Pin compatible with CY62138V ®
This is ideal for providing More Battery Life™ (MoBL ) in
• Ultra low standby power
portable applications such as cellular telephones. The device
also has an aut
Summary of the content on the page No. 2
® CY62138F MoBL [2] Pin Configuration 32-Pin SOIC/TSOP II Pinout Top View V A 1 CC 17 32 A A 16 2 31 15 A CE 14 3 30 2 A 12 4 29 WE A A 7 5 28 13 A A 6 6 27 8 A A 5 7 26 9 A A 4 8 25 11 A 3 9 24 OE A 2 10 A 23 10 A 1 11 22 CE 1 A 0 12 21 IO 7 IO 13 IO 0 20 6 IO 1 IO 14 19 5 IO 2 15 18 IO 4 V 16 17 SS IO 3 Product Portfolio Power Dissipation V Range (V) Operating I (mA) CC CC Speed Product Standby I (µA) SB2 (ns) f = 1MHz f = f max [3] [3] [3] [3] Min Typ Max Typ Max Typ Max Typ Max CY62138FLL
Summary of the content on the page No. 3
® CY62138F MoBL [4, 5] DC Input Voltage ............ –0.5V to 6.0V (V + 0.5V) Maximum Ratings CCmax Output Current into Outputs (LOW) ............................ 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage ......................................... > 2001V device. These user guidelines are not tested. (MIL–STD–883, Method 3015) Storage Temperature ................................ –65°C to + 150°C Latch-up Current ..................................
Summary of the content on the page No. 4
® CY62138F MoBL AC Test Loads and Waveforms R1 ALL INPUT PULSES V CC OUTPUT 3.0V 90% 90% 10% 10% R2 GND 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING JIG AND Equivalent to: THEVENIN EQUIVALENT SCOPE R TH OUTPUT V Parameters 5.0V Unit R1 1800 Ω R2 990 Ω R 639 Ω TH V 1.77 V TH Data Retention Characteristics (Over the Operating Range) [3] Parameter Description Conditions Min Typ Max Unit V V for Data Retention 2.0 V DR CC [7] I Data Retention Current V = V , CE > V − 0.2V or CE < 0.2V, 15
Summary of the content on the page No. 5
® CY62138F MoBL [11] Switching Characteristics (Over the Operating Range) 45 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 ns ACE 1 2 t OE LOW to Data Valid 22 ns DOE [12] t OE LOW to Low-Z 5ns LZOE [12, 13] t OE HIGH to High-Z 18 ns HZOE [12] t CE LOW and CE HIGH to Low Z 10 ns LZCE 1 2 [12, 13] t CE HIGH or CE LOW to High-Z 18 ns HZCE 1 2 t CE LOW a
Summary of the content on the page No. 6
® CY62138F MoBL Switching Waveforms [15, 16] Read Cycle 1 (Address transition controlled) tRC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [10, 16, 17] Read Cycle No. 2 (OE controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT t LZCE t PD I t V CC PU CC SUPPLY 50% 50% CURRENT I SB [10, 14, 18, 19] Write Cycle No. 1 (WE controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t HD DATA IO NOTE 20 DATA VALID
Summary of the content on the page No. 7
® CY62138F MoBL Switching Waveforms (continued) [10, 14, 18, 19] Write Cycle No. 2 (CE1 or CE2 controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t t SD HD DATA IO DATA VALID [10, 19] Write Cycle No. 3 (WE controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 20 DATA VALID DATA IO t t LZWE HZWE Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power Down Standby (I ) SB L H L Data Out Read Active (I ) CC L L X Data In Write Active (I ) CC L
Summary of the content on the page No. 8
® CY62138F MoBL Package Diagrams Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.118[2.997] 0.111[2.819] MAX. 0.004[0.102] 0.047[1.193] 0.004[0.102] 0.063[1.600] 0.050[1.270] MIN. 0.023[0.584] BSC. 0.039[0.990] 0.014[0.355] 0.020[0.508] 51-85081-*B SEATING PLANE Document #: 001-13194 Rev. *A Page 8 of 10 [+] Feedback
Summary of the content on the page No. 9
® CY62138F MoBL Package Diagrams (continued) Figure 2. 32-Pin TSOP II, 51-85095 51-85095-** MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-13194 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no res
Summary of the content on the page No. 10
® CY62138F MoBL Document History Page ® Document Title: CY62138F MoBL 2-Mbit (256K x 8) Static RAM Document Number: 001-13194 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 797956 See ECN VKN New Data Sheet *A 940341 See ECN VKN Added footnote #7 related to I and I SB2 CCDR Document #: 001-13194 Rev. *A Page 10 of 10 [+] Feedback
