Summary of the content on the page No. 1
CY7C67300
EZ-Host™ Programmable Embedded USB Host and
Peripheral Controller with Automotive AEC Grade Support
EZ-Host Features
■ Single chip programmable USB dual-role (Host/Peripheral) ■ On-chip 16-bit DMA/mailbox data path interface
controller with two configurable Serial Interface Engines (SIEs)
■ Supports 12 MHz external crystal or clock
and four USB ports
■ 3.3V operation
■ Support for USB On-The-Go (OTG) protocol
■ Automotive AEC grade option (–40°C to 85°C)
■ On-chip 48 MHz 16-bit proc
Summary of the content on the page No. 2
CY7C67300 Interrupts Introduction EZ-Host provides 128 interrupt vectors. The first 48 vectors are EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first hardware interrupts and the following 80 vectors are software full-speed, low cost multiport host/peripheral controller. EZ-Host interrupts. is designed to easily interface to most high performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC General Timers and Watchdog Timer processor to act as a coprocessor or operate
Summary of the content on the page No. 3
CY7C67300 Table 1. Interface Options for GPIO Pins (continued) GPIO Pins HPI IDE PWM HSS SPI UART I2C OTG [1] GPIO10 D10 D10 SCK [1] GPIO9 D9 D9 nSSI [1] GPIO8 D8 D8 MISO GPIO7 D7 D7 GPIO6 D6 D6 GPIO5 D5 D5 GPIO4 D4 D4 GPIO3 D3 D3 GPIO2 D2 D2 GPIO1 D1 D1 GPIO0 D0 D0 Table 2. Interface Options for External Memory Bus Pins MEM Pins HPI IDE PWM HSS SPI UART I2C OTG [2] D15 CTS [2] D14 RTS [2] D13 RXD [2] D12 TXD [2] D11 MOSI [2] D10 SCK [2] D9 nSSI [2] D8 MISO D[7:0] A[18:0] CONTROL USB Interf
Summary of the content on the page No. 4
CY7C67300 Table 3. USB Port Configuration Options (continued) Port Configurations Port 1A Port 1B Port 2A Port 2B 2 Hosts + 1 Peripheral Host Host Peripheral – 2 Hosts + 1 Peripheral Host Host – Peripheral 2 Hosts + 1 Peripheral Peripheral – Host Host 2 Hosts + 1 Peripheral – Peripheral Host Host 1 Host + 1 Peripheral Host – Peripheral – 1 Host + 1 Peripheral Host – – Peripheral 1 Host + 1 Peripheral – Host – Peripheral 1 Host + 1 Peripheral – Host Peripheral – 1 Host + 1 Peripheral Peripher
Summary of the content on the page No. 5
CY7C67300 Merge Mode External Memory Interface Merge modes enabled through the External Memory Control EZ-Host provides a robust interface to a wide variety of external register [0xC03A] allow combining of external memory regions in memory arrays. All available external memory array locations accordance with the following: can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF. ■ nXMEMSEL is active from 0x8000 to 0xBFFF External Me
Summary of the content on the page No. 6
CY7C67300 External Memory Interface Pins Table 6. External Memory Interface Pins (continued) Table 6. External Memory Interface Pins Pin Name Pin Number Pin Name Pin Number D3 80 nWR 64 D2 81 nRD 62 D1 82 nXMEMSEL (optional nCS) 34 D0 83 nXROMSEL (ROM nCS) 35 External Memory Interface Block Diagrams nXRAMSEL (RAM nCS) 36 Figure 2 illustrates how to connect a 64k × 8 memory array A18 95 (SRAM/ROM) to the EZ-Host external memory interface. A17 96 Figure 2. Interfacing to 64k × 8 Memory A
Summary of the content on the page No. 7
CY7C67300 2 Figure 4 illustrates the interface for connecting an 8-bit ROM or I C EEPROM Interface 8-bit RAM to the EZ-Host external memory interface. In 8-bit 2 EZ-Host provides a master-only I C interface for external serial mode, up to 512K bytes of external ROM or RAM are supported. EEPROMs. The serial EEPROM can be used to store application 2 specific code and data. Use the I C interface for loading code out Figure 4. Interfacing up to 512k × 8 for External Code/Data 2 2 of EEPROM, it is
Summary of the content on the page No. 8
CY7C67300 SPI Pins HSS Pins The SPI port has a few different pin location options as shown in The HSS port has a few different pin location options as shown Table 9. The port location is selectable via the GPIO control in Table 10. The port location is selectable via the GPIO control register [0xC006]. register [0xC006]. Table 10. HSS Interface Pins Table 9. SPI Interface Pins Pin Name Pin Number Pin Name Pin Number Default Location Default Location CTS 44 nSSI 56 or 65 RTS 53 SCK 61 RXD 54
Summary of the content on the page No. 9
CY7C67300 [3, 4] Table 12. HPI Interface Pins (continued) Host Port Interface EZ-Host has an HPI interface. The HPI interface provides DMA D11 60 access to the EZ-Host internal memory by an external host, plus D10 61 a bidirectional mailbox register for supporting high level commu- D9 65 nication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of D8 66 EZ-Host can be accomplished through this interface via an D7 86 extensible API
Summary of the content on the page No. 10
CY7C67300 Table 14. IDE Throughput ATA/ATAPI-4 Actual ATA/ATPI-4 Actual Mode Min Cycle Time Min Cycle Time Max Transfer Rate Max Transfer Rate PIO Mode 0 600 ns 30T = 625 ns 3.33 MB/s 3.2 MB/s PIO Mode 1 383 ns 20T = 416.7 ns 5.22 MB/s 4.8 MB/s PIO Mode 2 240 13T = 270.8 ns 8.33 MB/s 7.38 MB/s PIO Mode 3 180 ns 10T = 208.3 ns 11.11 MB/s 9.6 MB/s PIO Mode 4 120 ns 8T = 166.7 ns 16.67 MB/s 12.0 MB/s T = System clock period = 1/48 MHz. IDE Features Charge Pump Interface VBUS for the USB OTG por
Summary of the content on the page No. 11
CY7C67300 Booster Pins Booster Interface EZ-Host has an on chip power booster circuit for use with power Table 17. Charge Pump Interface Pins supplies that range between 2.7V and 3.6V. The booster circuit Pin Name Pin Number boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and BOOSTVcc 16 capacitor. During power down mode, the circuit is disabled to VSWITCH 14 save power. Figure 6 shows how to connect the booster c
Summary of the content on the page No. 12
CY7C67300 Boot Configuration Interface Operational Modes EZ-Host can boot into any one of four modes. The mode it boots The operational modes are discussed in the following sections. into is determined by the TTL voltage level of GPIO[31:30] at the Coprocessor Mode time nRESET is deasserted. Table 19 shows the different boot pin combinations possible. After a reset pin event occurs, the EZ-Host can act as a coprocessor to an external host processor. BIOS bootup procedure executes for up to 3 m
Summary of the content on the page No. 13
CY7C67300 Minimum Hardware Requirements for Standalone Mode – Peripheral Only Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only EZ-Host CY7C67300 Reset VReg VCC, AVCC, nRESET Logic BoostVCC VBus D+ DPlus Standard-B DMinus D- or Mini-B GND SHIELD VCC Bootstrap Options 47Kohm Vcc Vcc Pin 38 10k 10k GPIO[30] SCL* GPIO[31] SDA* Int. 16k x8 Code / Data Bootloading Firmware VCC A0 Up to 64k x8 VCC EEPROM A1 WP A2 SCL Reserved 22pf GND SDA XIN GND, AGND, 12MHz BoostGND XOUT 22pf
Summary of the content on the page No. 14
CY7C67300 External (Remote) Wakeup Source Memory Map There are several possible events available to wake EZ-Host The memory map is discussed in the following sections. from Sleep mode as shown in Table 20. These may also be used as remote wakeup options for USB applications. See the Power Mapping Control Register [0xC00A] [R/W] on page 19 for details. The total memory space directly addressable by the CY16 Upon wakeup, code begins executing within 200 µs, the time it processor is 64K (0x0000-0
Summary of the content on the page No. 15
CY7C67300 Figure 10. Memory Map Internal Memory HW INT's 0x0000 - 0x00FF SW INT's 0x0100 - 0x011F Primary Registers Swap Registers 0x0120 - 0x013F HPI Int / Mailbox 0x0140 - 0x0148 0x014A - 0x01FF LCP Variables 0x0200 - 0x02FF USB Registers 0x0300 - 0x030F Slave Setup Packet 0x0310 - 0x03FF BIOS Stack 0x0400 - 0x04A2 USB Slave & OTG USER SPACE 0x04A4 - 0x3FFF ~15K External Memory USER SPACE 0x4000 - 0x7FFF 16K Bank Selected Extended Page 1 by 0x8000 - 0x9FFF USER SPACE 01 0xC018 Up to 64
Summary of the content on the page No. 16
CY7C67300 Registers Table 21. Processor Control Registers Register Name Address R/W Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers CPU Flags Register 0xC000 R of this type have multiple definitions for the same address. Register Bank Register 0xC002 R/W The default register values listed in this data sheet may be Hardware Revision Register 0xC004 R altered to some other value during the BIOS initialization. Refer CPU
Summary of the content on the page No. 17
CY7C67300 Bank Register [0xC002] [R/W] Table 23. Bank Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 Bit # 7 6 5 4 3 2 1 0 Field ...Address Reserved Read/Write R/W R/W R/W - - - - - Default 0 0 0 X X X X X Register Description The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0–R15. A register address is automatically generated by: 1. Shifting
Summary of the content on the page No. 18
CY7C67300 CPU Speed Register [0xC008] [R/W] Table 26. CPU Speed Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved CPU Speed Read/Write - - - - R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU, all other peripheral timing is still based on the 48 MHz system clock (unless
Summary of the content on the page No. 19
CY7C67300 Power Control Register [0xC00A] [R/W] Table 28. Power Control Register Bit # 15 14 13 12 11 10 9 8 Host/Device Host/Device Host/Device Host/Device OTG Reserved HSS SPI 2B 2A 1B 1A Wake Wake Wake Wake Wake Wake Wake Enable Enable Enable Field Enable Enable Enable Enable Read/Write R/W R/W R/W R/W R/W - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 HPI Reserved GPI Reserved Boost 3V Sleep Halt Wake Wake OK Enable Enable Field Enable Enable Read/Write R/W - - R/W - R R/W R/W
Summary of the content on the page No. 20
CY7C67300 Boost 3V OK (Bit 2) Halt Enable (Bit 0) The Boost 3V OK bit is a read only bit that returns the status of Setting this bit to ‘1’ immediately initiates HALT mode. While in the OTG Boost circuit. HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The 1: Boost circuit not ok and internal voltage rails are below 3.0V power saving using HALT in most cases is minimal, but in appli- 0: Boost circuit ok and interna
