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CY8C23433, CY8C23533
®
PSoC Programmable System-on-Chip™
Features
■ Powerful Harvard Architecture Processor ■ Complete Development Tools
❐ M8C Processor Speeds to 24 MHz ❐ Free Development Software (PSoC Designer™)
❐ 8x8 Multiply, 32-Bit Accumulate ❐ Full-Featured In-Circuit Emulator and Programmer
❐ Low Power at High Speed ❐ Full Speed Emulation
❐ 3.0 to 5.25V Operating Voltage ❐ Complex Breakpoint Structure
❐ Industrial Temperature Range: -40°C to +85°C ❐ 128K Bytes Trace Memory
■ Advanced Per
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Row Output Configuration Digital Clocks From Core CY8C23433, CY8C23533 PSoC Functional Overview Digital System The PSoC family consists of many mixed-signal array with The Digital System consists of 4 digital PSoC blocks. Each block On-Chip Controller devices. These devices are designed to is an 8-bit resource that is used alone or combined with other replace multiple traditional MCU-based system components with blocks to form 8, 16, 24, and 32-bit peripherals, which are called a low cost single
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CY8C23433, CY8C23533 Figure 2. Analog System Block Diagram Analog System P0[7] P0[6] The Analog system consists of an 8-bit SAR ADC and four configurable blocks. The programmable 8-bit SAR ADC is an P0[5] P0[4] optimized ADC that runs up to 300 Ksps, with monotonic guarantee. It also has the features to support a motor control P0[3] P0[2] application. P0[1] P0[0] Each analog block consists of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are P2[6] ver
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CY8C23433, CY8C23533 Additional System Resources Getting Started System Resources, some of which are listed in the previous The quickest path to understanding the PSoC silicon is by sections, provide additional capability useful to complete reading this data sheet and using the PSoC Designer Integrated systems. Additional resources include a multiplier, decimator, Development Environment (IDE). This data sheet is an overview low voltage detection, and power on reset. Brief statements of the PSoC
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Results CY8C23433, CY8C23533 PSoC Designer Software Subsystems Development Tools ® Device Editor PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable The Device Editor subsystem allows the user to select different System-on-Chip (PSoC) devices. The PSoC Designer IDE and onboard analog and digital components called user modules application runs on Windows NT 4.0, Windows 2000, Windows using the PSoC blocks. Examples of user modules are ADCs, Millenni
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CY8C23433, CY8C23533 Debugger of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also The PSoC Designer Debugger subsystem provides hardware provide tested software to cut your development time. The user in-circuit emulation, allowing the designer to test the program in module application programming interface (API) provides high a physical system while providing an internal view of the PSoC level functions to control and respond to har
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CY8C23433, CY8C23533 The next step is to write your main program, and any Table 2. Acronyms Used (continued) sub-routines using PSoC Designer’s Application Editor Acronym Description subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including PWM pulse width modulator all generated code files) from a hierarchal view. The source code RAM random access memory editor provides syntax coloring and advanced edit features for ROM read
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CY8C23433, CY8C23533 Pinouts The PSoC CY8C23X33 is available in 32-pin QFN and 28-pin SSOP packages. Every port pin (labeled with a “P”), except for Vss and Vdd in the following table and figure, is capable of Digital IO. 32-Pin Part Pinout Table 3. Pin Definitions - 32-Pin (QFN) Type Figure 5. CY8C23533 32-Pin PSoC Device Pin Pin Description No. Name Digital Analog 1 IO P2[7] GPIO 2 IO P2[5] GPIO 3 IO I P2[3] Direct Switched Capacitor Block Input GPIO, P2[7] 1 P0[2], A, I 24 GPIO, P2[5] 2
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CY8C23433, CY8C23533 28-Pin Part Pinout Table 4. Pin Definitions - 28-Pin (SSOP) Figure 6. CY8C23433 28-Pin PSoC Device Description AIO, P0[7] 1 28 Vdd IO, P0[5] 2 27 P0[6], AIO, AnColMux and ADC IP IO, P0[3] 3 26 P0[4], AIO, AnColMux and ADC IP AIO, P0[1] 4 25 P0[2], AIO, AnColMux and ADC IP 1 IO I P0[7] Analog Column Mux IP and ADC IP 5 24 P0[0], AIO, AnColMux and ADC IP IO, P2[7] IO, P2[5] 6 23 P2[6], VREF 2 IO IO P0[5] Analog Column Mux IP and Column AIO, P2[3] 7 22 P2[4], AGND S
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CY8C23433, CY8C23533 Register Mapping Tables Register Reference The PSoC device has a total register address space of 512 This section lists the registers of the CY8C23433 PSoC device bytes. The register space is referred to as IO space and is by using mapping tables, in offset order. divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit Register Conventions is set the user is in Bank 1. Abbreviations Used Note In the f
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CY8C23433, CY8C23533 Table 6. Register Map Bank 0 Table: User Space PRT0DR 00 RW 40 80 C0 PRT0IE 01 RW 41 81 C1 PRT0GS 02 RW 42 82 C2 PRT0DM2 03 RW 43 83 C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB PRT3DR 0C RW 4C 8C CC PRT3IE 0D RW 4D 8D CD PRT3GS 0E RW 4E 8E CE PRT3DM2 0F RW 4F 8F CF 10 50 90 D0 11 51 91 D1 12
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CY8C23433, CY8C23533 Table 6. Register Map Bank 0 Table: User Space (continued) 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Gray fields are reserved. # Access is bit specific. Table 7. Register Map Bank 1 Table: Configuration Space PRT0DM0 00 RW 40 80 C0 PRT0DM1 01 RW 41 81 C1 PRT0IC0 02 RW 42 82 C2 PRT0IC1 03 RW 43 83 C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW 48 88 C8 P
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CY8C23433, CY8C23533 Table 7. Register Map Bank 1 Table: Configuration Space (continued) 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 * 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FLS_PR1 FA RW 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Gray fields are reserved. # Access is bit specific. Document Number: 001-44369 Rev. *B Page 13 of 37 [+] Feedback Name Addr (1,Hex) Access Name Addr (1,Hex) Access Nam
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Vdd Voltage Vdd Voltage Valid Operating Region CY8C23433, CY8C23533 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C23433 PSoC device. For the latest electrical specifications, visit http://www.cypress.com/psoc. Specifications are valid for -40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Refer to A J Table 24 on page 25 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 7. Voltage versus CPU F
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CY8C23433, CY8C23533 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes T Storage Temperature -55 25 +100 °C Higher storage temperatures STG reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrade reliability. T Ambient Temperature with Power Applied -40 – +85
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CY8C23433, CY8C23533 DC Electrical Characteristics DC Chip-Level Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only. Table 11. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 3.0 – 5.25 V See DC POR
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CY8C23433, CY8C23533 DC General Purpose IO Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only. Table 12. 5V and 3.3V DC GPIO Specifications Symbol Description Min Typ Max Units Notes R Pull up Resistor 4 5.6 8 kΩ PU R Pull down Resistor 4 5.6
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CY8C23433, CY8C23533 DC Operational Amplifier Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed spe
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CY8C23433, CY8C23533 Table 14. 3.3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input Offset Voltage (absolute value) OSOA Power = Low, Opamp Bias = High – 1.65 10 mV Power = Medium, Opamp Bias = High – 1.32 8 mV High Power is 5 Volts Only TCV Average Input Offset Voltage Drift – 7.0 35.0 μV/°C OSOA I Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA. EBOA C Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin
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CY8C23433, CY8C23533 DC Analog Output Buffer Specifications The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only. Table 16. 5V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes V Input Offset Voltage (Absolute Value) – 3 12 mV O
