Summary of the content on the page No. 1
CY7C2561KV18, CY7C2576KV18
PRELIMINARY
CY7C2563KV18, CY7C2565KV18
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
Features Configurations
■ Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles:
❐ Supports concurrent transactions
CY7C2561KV18 – 8M x 8
■ 550 MHz clock for high bandwidth
CY7C2576KV18 – 8M x 9
CY7C2563KV18 – 4M x 18
■ 4-word burst for reducing address bus frequency
CY7C2565KV18 – 2M x 36
■ Double Data Rate (DDR) inte
Summary of the content on the page No. 2
2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Logic Block Diagram (CY7C2561KV18) 8 D [7:0] Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 32 V 16 REF 8 CQ Reg. Reg. Control 8 WPS Logic 8 16 8 Q NWS Reg. [7:0] [1:0] 8 QVLD Logic Block Diagram (CY7C2576KV18) 9 D [8:0] Writ
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1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Logic Block Diagram (CY7C2563KV18) 18 D [17:0] Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control WPS 18 Logic 18 18 36 BWS Q Reg. [1:0] [17:0] 18 QVLD Logic Block Diagram (CY7C
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Pin Configuration [2] The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C2561KV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ AA WPS NWS K NC/144M RPS AA CQ 1 B NC NC NC A NC/288M K NWS ANC NC Q3 0 C NC NC NC V ANC A V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Pin Configuration [2] The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow. (continued) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C2563KV18 (4M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M A WPS BWS K NC/288M RPS AA CQ 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 V ANC A V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Table 2. Pin Definitions Pin Name IO Pin Description D Input- Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. [x:0] Synchronous CY7C2561KV18 − D [7:0] CY7C2576KV18 − D [8:0] CY7C2563KV18 − D [17:0] CY7C2565KV18 − D [35:0] WPS Input- Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated.
Summary of the content on the page No. 7
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Table 2. Pin Definitions (continued) Pin Name IO Pin Description K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q . All accesses are initiated on the rising edge of K. [x:0] K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q . [x:0] CQ Ec
Summary of the content on the page No. 8
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 clock rise. Doing so pipelines the data flow such that data is Functional Overview transferred out of the device on every rising edge of the input The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, clocks (K and K). CY7C2565KV18 are synchronous pipelined Burst SRAMs When the read port is deselected, the CY7C2563KV18 first equipped with a read port and a write port. The read port is completes the pending read transactions. Synchronous
Summary of the content on the page No. 9
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Read access and write access must be scheduled such that one Valid Data Indicator (QVLD) transaction is initiated on any clock cycle. If both ports are QVLD is provided on the QDR-II+ to simplify data capture on high selected on the same K clock rise, the arbitration depends on the speed systems. The QVLD is generated by the QDR-II+ device previous state of the SRAM. If both ports are deselected, the along with data output. This s
Summary of the content on the page No. 10
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Application Example Figure 1 shows two QDR-II+ used in an application. Figure 1. Application Example RQ = 250ohms RQ = 250ohms ZQ ZQ ODT ODT SRAM #1 SRAM #2 Vt CQ/CQ CQ/CQ D Q D Q R A RPS WPS BWS K K A K K RPS WPS BWS DATA IN R DATA OUT Vt Address Vt R RPS BUS MASTER WPS (CPU or ASIC) BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 Source K Source K R ODT R = 50ohms, Vt = V /2 DDQ Table 3. Truth Table [4, 5, 6, 7, 8, 9] The truth table
Summary of the content on the page No. 11
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Table 4. Write Cycle Descriptions [4, 12] The write cycle description table for CY7C2561KV18 and CY7C2563KV18 follows. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L–H – During the data portion of a write sequence: CY7C2561KV18 − both nibbles (D ) are written into the device. [7:0] CY7C2563KV18 − both bytes (D ) are written into the device. [17:0] L L – L-H During the data portion of a write sequence: CY7C2561KV18 − both nibb
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Table 6. Write Cycle Descriptions [4, 12] The write cycle description table for CY7C2565KV18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 ) are written into LLLL L–H – During the data portion of a write sequence, all four bytes (D [35:0] the device. LLLL – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only th
Summary of the content on the page No. 13
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDE
Summary of the content on the page No. 14
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Figure 2. TAP Controller State Diagram [13] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 13. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Docum
Summary of the content on the page No. 16
CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Figure 3. TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 108 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [14, 15, 16] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I =
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 TAP AC Switching Characteristics [17, 18] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Table 7. Identification Register Definitions Value Instruction Field Description CY7C2561KV18 CY7C2576KV18 CY7C2563KV18 CY7C2565KV18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010010001000100 11010010001001100 11010010001010100 11010010001100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor.
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CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 Table 10. Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 1
Summary of the content on the page No. 20
~ ~ CY7C2561KV18, CY7C2576KV18 PRELIMINARY CY7C2563KV18, CY7C2565KV18 PLL Constraints Power Up Sequence in QDR-II+ SRAM ■ PLL uses K clock as its synchronizing input. The input must QDR-II+ SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The PLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the PLL is enabled, then the ■ Apply power and d
