Summary of the content on the page No. 1
CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
18-Mbit DDR-II SRAM 4-Word
Burst Architecture
Features Functional Description
■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and
CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs
■ 300 MHz clock for high bandwidth
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
■ 4-word burst for reducing address bus frequency
a two
Summary of the content on the page No. 2
512K x 8 Array 512K x 9 Array 512K x 8 Array 512K x 9 Array 512K x 8 Array 512K x 9 Array 512K x 8 Array 512K x 9 Array CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Logic Block Diagram (CY7C1317CV18) Write Write Write Write 19 A Reg Reg Reg Reg (18:0) Address Register 8 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 32 CQ V 16 8 REF Reg. CQ Control Reg. 8 R/W Logic 8 16 NWS 8 [1:0] Reg. DQ [7:0] 8 Logic Block Diagram (CY7C1917CV18) Write Write Write Write 19 A Reg Reg
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256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Logic Block Diagram (CY7C1319CV18) Burst A (1:0) Logic 2 Write Write Write Write 20 18 A Reg Reg Reg Reg (19:0) A Address (19:2) Register 18 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 72 CQ V 36 18 REF Reg. CQ Control Reg. 18 R/W Logic 18 36 BWS 18 [1:0] Reg. DQ [17:0] 18 Logic Block Diagram (CY
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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Configuration [1] The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1317CV18 (2M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W NWS K NC/144M LD A NC/36M CQ 1 B NC NC NC A NC/288M K NWS ANC NC DQ3 0 C NC NC NC V ANC A V NC NC NC SS SS D NC NC NC V V V V V NC NC NC SS SS SS SS SS E NC NC DQ4 V V V V V NC NC DQ2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC
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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Configuration (continued) [1] The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1319CV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS K NC/144M LD A NC/36M CQ 1 B NC DQ9 NC A NC/288M K BWS ANC NC DQ8 0 C NC NC NC V AA0 A1 V NC DQ7 NC SS SS D NC NC DQ10 V V V V V NC NC NC SS SS SS SS SS E NC NC DQ11 V V V V V NC NC DQ6 DDQ SS SS SS DDQ F NC
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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Definitions Pin Name IO Pin Description DQ Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write [x:0] Synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q are automatically
Summary of the content on the page No. 7
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Pin Definitions (continued) Pin Name IO Pin Description CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 24. CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized
Summary of the content on the page No. 8
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Write Operations Functional Overview Write operations are initiated by asserting R/W LOW and LD The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and LOW at the rising edge of the positive input clock (K). The CY7C1321CV18 are synchronous pipelined Burst SRAMs address presented to address inputs is stored in the write equipped with a DDR interface, which operates with a read address register and the least two significant bits of the address lat
Summary of the content on the page No. 9
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 after the read(s), the stored data from the earlier write is written Echo Clocks into the SRAM array. This is called a posted write. Echo clocks are provided on the DDR-II to simplify data capture If a read is performed on the same address on which a write is on high-speed systems. Two echo clocks are generated by the performed in the previous cycle, the SRAM reads out the most DDR-II. CQ is referenced with respect to C and CQ is referenced c
Summary of the content on the page No. 10
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Application Example Figure 1 shows two DDR-II used in an application. Figure 1. Application Example R = 250ohms R = 250ohms SRAM#2 SRAM#1 ZQ ZQ DQ DQ CQ/CQ# CQ/CQ# A LD# R/W# C C# K K# A LD# R/W# C C# K K# DQ Addresses BUS Cycle Start# MASTER R/W# (CPU Return CLK or Vterm = 0.75V Source CLK ASIC) R = 50ohms Return CLK# Vterm = 0.75V Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2 Truth Table [2, 3, 4, 5, 6, 7] The truth
Summary of the content on the page No. 11
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Burst Address Table (CY7C1319CV18, CY7C1321CV18) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X..X00 X..X01 X..X10 X..X11 X..X01 X..X10 X..X11 X..X00 X..X10 X..X11 X..X00 X..X01 X..X11 X..X00 X..X01 X..X10 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1317CV18 and CY7C1319CV18 follows. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L–H – During the data por
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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1321CV18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L–H – During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. LLLL – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is wr
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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 16. U
Summary of the content on the page No. 14
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TA
Summary of the content on the page No. 15
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-07161 Rev
Summary of the content on the page No. 16
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 106 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH
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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capt
Summary of the content on the page No. 18
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Identification Register Definitions Value Instruction Field Description CY7C1317CV18 CY7C1917CV18 CY7C1319CV18 CY7C1321CV18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010100011000101 11010100011001101 11010100011010101 11010100011100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indi
Summary of the content on the page No. 19
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P29 9G 57 5B85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N32 9F 60 5C88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43
Summary of the content on the page No. 20
~ ~ CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 DLL Constraints Power Up Sequence in DDR-II SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR-II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The DLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the DLL is enabled, then the ■ Apply power and drive DOFF eith
