Summary of the content on the page No. 1
CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
CY7C145, CY7C144
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features Functional Description
■ True Dual-Ported memory cells that enable simultaneous The CY7C144 and CY7C145 are high speed CMOS 8K x 8
reads of the same memory location and 8K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C144/5 to handle situations when
■ 8K x 8 organization (CY7C144)
multiple processors access the same piece
Summary of the content on the page No. 2
CY7C145, CY7C144 Pin Configurations Figure 1. 68-Pin PLCC (Top View) 98 7 6 5 4 3 2 168 6766 65646362 61 I/O 2L A 10 60 5L I/O 3L A 11 59 4L I/O A 4L 12 58 3L I/O 5L 13 57 A 2L GND A 14 56 1L I/O 6L A 15 55 0L I/O 7L INT 16 54 L V CC 17 53 BUSY L CY7C144/5 GND 18 52 GND I/O 0R 19 51 M/S I/O 1R BUSY 20 50 R I/O 2R 49 21 INT R V CC 48 A 0R 22 I/O 3R 23 47 A 1R I/O 4R 24 46 A 2R I/O 5R 25 45 A 3R I/O 6R A 26 44 4R 2728 29 303132 3334 353637 3839 4041 4243 Figure 2. 64-Pin PLCC (Top View) Notes
Summary of the content on the page No. 3
CY7C145, CY7C144 Pin Configurations (continued) Figure 3. 80-Pin TQFP NC 1 60 NC /O 2L A 2 5L 59 /O A 4L 3L 3 58 /O 4 A 4L 57 3L A /O 5 2L 5L 56 A GND 6 1L 55 /O A 0L 6L 7 54 /O INT 7L 8 53 L BUSY V L CC 9 52 GND NC 10 CY7C145 51 M/S GND 11 50 /O 0R BUSY 12 R 49 /O 1R INT 13 48 R /O 2R A 14 47 0R V CC A 15 1R 46 /O 3R 16 A 45 2R /O A 4R 17 3R 44 O A 5R 18 4R 43 /O 6R 19 NC 42 NC 20 NC 41 Table 1. Pin Definitions Left Port Right Port Description I/O Data bus Input/Output I/O 0L −7L(8L) 0R −7
Summary of the content on the page No. 4
CY7C145, CY7C144 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage........................................... >2001V Exceeding maximum ratings may impair the useful life of the (per MIL-STD-883, Method 3015) [5] device. These user guidelines are not tested. Latch-Up Current.................................................... >200 mA Storage Temperature . .. ... .. .. .. .. ... .. .. .. ... .. .. .. .. ... −65 °C to +150 °C Ambient Tem
Summary of the content on the page No. 5
CY7C145, CY7C144 Electrical Characteristics Over the Operating Range (continued) 7C144-35 7C144-55 7C145-35 7C145-55 Parameter Description Test Conditions Unit Min Max Min Max V Output HIGH Voltage V = Min., I = −4.0 mA 2.4 2.4 V OH CC OH V Output LOW Voltage V = Min., I = 4.0 mA 0.4 0.4 V OL CC OL V Input HIGH Voltage 2.2 2.2 V IH V Input LOW Voltage 0.8 0.8 V IL I Input Leakage Current GND < V < V −10 +10 −10 +10 μA IX I CC I Output Leakage Current Outputs Disabled, GND < V < V −10 +10 −10 +
Summary of the content on the page No. 6
CY7C145, CY7C144 Figure 4. AC Test Loads and Waveforms 5V 5V R1 = 893 Ω R1 = 893 Ω R = 250 Ω TH OUTPUT OUTPUT OUTPUT C= 30 pF C = 30pF C= 5pF R = 347 Ω R2 = 347 Ω V = 1.4V TH (a) Normal Load (Load1) (b) Th évenin Equivalent (Load 1) (c) Three-State Delay (Load 3) ALL INPUT PULSES OUTPUT 3.0V 90% 90% 10% 10% C= 30pF GND ≤ 3 ns ≤ 3ns Load (Load 2) [9] Switching Characteristics Over the Operating Range 7C144-15 7C144-25 7C144-35 7C144-55 7C145-15 7C145-25 7C145-35 7C145-55 Parameter Description
Summary of the content on the page No. 7
CY7C145, CY7C144 [9] Switching Characteristics Over the Operating Range (continued) 7C144-15 7C144-25 7C144-35 7C144-55 7C145-15 7C145-25 7C145-35 7C145-55 Parameter Description Unit Min Max Min Max Min Max Min Max t Data Set-Up to Write End 10 15 15 25 ns SD t Data Hold From Write End 0 0 0 0 ns HD [11,12] t R/W LOW to High Z 10 15 20 25 ns HZWE [11,12] t R/W HIGH to Low Z 3 3 3 3 ns LZWE [13] t Write Pulse to Data Delay 30 50 60 70 ns WDD [13] t Write Data Valid to Read Data 25 30 35 40 ns
Summary of the content on the page No. 8
CY7C145, CY7C144 Switching Waveforms [15, 16] Figure 5. Read Cycle No. 1 (Either Port Address Access) t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 17, 18] Figure 6. Read Cycle No. 2 (Either Port CE/OE Access) SEM or CE t HZCE t ACE OE t HZOE t DOE t LZOE t LZCE DATA VALID DATA OUT t PU t PD I CC I SB [19, 20] Figure 7. Read Timing with Port-to-Port Delay (M/S=L) t WC ADDRESS R MATCH t PWE R/W R t t SD HD DATAIN VALID R ADDRESS L MATCH t DDD DATA VALID OUTL t WDD Not
Summary of the content on the page No. 9
CY7C145, CY7C144 Switching Waveforms (continued) [21, 22, 23] Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port) t WC ADDRESS t SCE SEM OR CE t t HA AW t PWE R/W t t t SA SD HD DATA IN DATA VALID OE t t HZOE LZOE HIGH IMPEDANCE DATA OUT [21, 23, 24] Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port) t WC ADDRESS t t SCE HA OR CE SEM t AW t SA t PWE R/W t t SD HD DATAVALID DATA IN t t LZWE HZWE HIGH IMPEDANCE DATA OUT Notes 21. The internal write time of th
Summary of the content on the page No. 10
CY7C145, CY7C144 Switching Waveforms (continued) [25] Figure 10. Semaphore Read After Write Timing, Either Side t t AA OHA A −A VALID ADDRESS VALID ADDRESS 0 2 t AW t ACE t HA SEM t t SCE SOP t SD I/O 0 DATA VALID IN DATA VALID OUT t HD t t SA PWE R/W t t SWRD DOE t OE SOP WRITE CYCLE READ CYCLE [26, 27, 28] Figure 11. Semaphore Contention A −A 0L 2L MATCH R/W L SEM L t SPS A −A 0R 2R MATCH R/W R SEM R Notes 25. CE = HIGH for the duration of the above timing (both write and read cycle). 26.
Summary of the content on the page No. 11
CY7C145, CY7C144 Switching Waveforms (continued) [20] Figure 12. Read with BUSY (M/S=HIGH) t WC ADDRESS R MATCH t PWE R/W R t t SD HD DATAIN VALID R t PS ADDRESS L MATCH t BLA t BHA BUSY L t BDD t DDD DATA VALID OUTL t WDD Figure 13. Write Timing with Busy Input (M/S=LOW) t PWE R/W t t WB WH BUSY Document #: 38-06034 Rev. *D Page 11 of 21 [+] Feedback
Summary of the content on the page No. 12
CY7C145, CY7C144 Switching Waveforms (continued) [29] Figure 14. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L,R ADDRESS MATCH CE L t PS CE R t t BLC BHC BUSY R CE Valid First: R ADDRESS ADDRESS MATCH L,R CE R t PS CE L t t BLC BHC BUSY L [29] Figure 15. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: t or t RC WC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH t PS ADDRESS R t t BLA BHA BUSY R Right Address Valid First: t or t RC WC ADDRESS R A
Summary of the content on the page No. 13
CY7C145, CY7C144 Switching Waveforms (continued) Figure 16. Interrupt Timing Diagrams Left Side Sets INT : R t WC ADDRESS WRITE 1FFF L [30] t HA CE L R/W L INT R [31] t INS Right Side Clears INT : R t RC ADDRESS READ 1FFF R CE R [31] t INR R/W R OE R INT R Right Side Sets INT : L t WC ADDRESS R WRITE 1FFE [30] t HA CE R R/W R INT L [31] t INS Left Side Clears INT : L t RC ADDRESS R READ 1FFE CE L [31] t INR R/W L OE L INT L Notes 30. t depends on which enable pin (CE or R/W ) is deasserted f
Summary of the content on the page No. 14
CY7C145, CY7C144 Master/Slave Architecture An M/S pin is provided in order to expand the word width by The CY7C144/5 consists of a an array of 8K words of 8/9 bits configuring the device as either a master or a slave. The BUSY each of dual-port RAM cells, I/O and address lines, and control output of the master is connected to the BUSY input of the signals (CE, OE, R/W). These control pins permit independent slave. This enables the device to interface to a master device access for reads or writ
Summary of the content on the page No. 15
CY7C145, CY7C144 Table 3. Non-Contending Read/Write Inputs Outputs CE R/W OE SEM I/O Operation 0 −7/8 H X X H High Z Power-Down H H L L Data Out Read Data in Semaphore X X H X High Z I/O Lines Disabled H X L Data In Write to Semaphore LH L H Data Out Read LL X H Data In Write L X X L Illegal Condition Table 4. Interrupt Operation Example (assumes BUSY = BUSY = HIGH) L R Function Left Port Right Port R/W CE OE A INT R/W CE OE A INT 0 −12 0 −12 Set Left INT X X X X L L L X 1FFE X Reset Left I
Summary of the content on the page No. 16
CY7C145, CY7C144 Figure 17. Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT NORMALIZED SUPPLY CURRENT vs. OUTPUT VOLTAGE vs. AMBIENT TEMPERATURE vs. SUPPLY VOLTAGE 200 1.4 1.2 I CC 1.2 1.0 I 160 CC 1.0 I 0.8 SB3 I SB3 120 0.8 0.6 V = 5.0V CC V = 5.0V CC 0.6 80 T = 25°C A V = 5.0V IN 0.4 0.4 40 0.2 0.2 0 0.6 0.0 5.0 4.0 4.5 5.0 5.5 6.0 −55 25 125 0 1.0 2.0 3.0 4.0 AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME OUTPUT
Summary of the content on the page No. 17
CY7C145, CY7C144 Ordering Information 8K x8 Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 15 CY7C144-15AC A65 64-Pin Thin Quad Flat Pack Commercial CY7C144-15AXC A65 64-Pin Pb-Free Thin Quad Flat Pack CY7C144-15JC J81 68-Pin Plastic Leaded Chip Carrier CY7C144-15JXC J81 68-Pin Pb-Free Plastic Leaded Chip Carrier CY7C144-15AI A65 64-Pin Thin Quad Flat Pack Industrial CY7C144-15JXI J81 68-Pin Pb-Free Plastic Leaded Chip Carrier CY7C144-15AXI A65 64-Pin Pb-Free
Summary of the content on the page No. 18
CY7C145, CY7C144 8K x9 Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 15 CY7C145-15AC A80 80-Pin Thin Quad Flat Pack Commercial CY7C145-15AXC A80 80-Pin Pb-Free Thin Quad Flat Pack CY7C145-15JC J81 68-Pin Plastic Leaded Chip Carrier 25 CY7C145-25AC A80 80-Pin Thin Quad Flat Pack Commercial CY7C145-25JC J81 68-Pin Plastic Leaded Chip Carrier CY7C145-25AI A80 80-Pin Thin Quad Flat Pack Industrial CY7C145-25JI J81 68-Pin Plastic Leaded Chip Carrier 35 CY7C145-35
Summary of the content on the page No. 19
CY7C145, CY7C144 Package Diagrams Figure 18. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 (51-85046) 51-85046-*C Document #: 38-06034 Rev. *D Page 19 of 21 [+] Feedback
Summary of the content on the page No. 20
CY7C145, CY7C144 Figure 19. 80-Pin Thin Plastic Quad Flat Pack A80 (51-85065) 51-85065-*B Figure 20. 68-Pin Plastic Leaded Chip Carrier J81 (51-85005) 51-85005-*A Document #: 38-06034 Rev. *D Page 20 of 21 [+] Feedback
