Summary of the content on the page No. 1
50
CY7C150
1Kx4 Static RAM
Separate I/O paths eliminates the need to multiplex data in
Features
and data out, providing for simpler board layout and faster sys-
• Memory reset function tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
1024 x 4 static RAM for control store in high-speed com-
for easy memory expansion.
puters
CMOS for optimum speed/power
Reset is initiated by selecting the device (CS = LOW) and tak-
ing
Summary of the content on the page No. 2
CY7C150 Static Discharge Voltage .......................................... >2001V Maximum Ratings (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guide- Latch-Up Current.................................................... >200 mA lines, not tested.) Storage Temperature ......................................−65°C to+150°C Operating Range Ambient Temperature with Ambient Power Applied...................................................−55°C to+125°C Range Te
Summary of the content on the page No. 3
CY7C150 [2,5] Switching Characteristics Over the Operating Range 7C150−10 7C150−12 7C150−15 7C150−25 7C150−35 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE t Read Cycle Time 10 12 15 25 35 ns RC t Address to Data Valid 10 12 15 25 35 ns AA t Output Hold from Address 2 2 2 2 2 ns OHA Change t CS LOW to Data Valid 8 10 12 15 20 ns ACS [6] t CS LOW to Low Z 0 0 0 0 0 ns LZCS [6,7] t CS HIGH to High Z 6 8 11 20 25 ns HZCS t OE LOW to Data Valid 6 8 10 15 2
Summary of the content on the page No. 4
CY7C150 Switching Waveforms [9,10] Read Cycle No.1 t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID C150-5 [9,11] Read CycleNo. 2 t RC CE t ACS OE t HZOE t DOE t HZCS t LZOE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT DATA VALID t LZCS C150-6 [8] Write CycleNo.1 (WEControlled) t WC ADDRESS t SCS CE t t AW HA t SA t PWE WE t t SD HD DATA IN DATA VALID IN t t HZWE LZWE HIGH IMPEDANCE DATA I/O DATA UNDEFINED C150-7 Notes: 9. WE is HIGH for read cycle. 10. Device is continuously select
Summary of the content on the page No. 5
CY7C150 Switching Waveforms (continued) [8,12] Write Cycle No.2(CS Controlled) t WC ADDRESS t t SA SCS CE t t AW HA t PWE WE t t HD SD DATA VALID DATA IN IN t HZWE HIGH IMPEDANCE DATA I/O DATA UNDEFINED C150-8 [13] Reset Cycle t RRC ADDRESS t SAR t HAR WE t t SWER HWER t t HCSR CS SCSR t PRS RESET t t HZRS LZRS DATA I/O HIGH IMPEDANCE OUTPUT VALID ZERO C150-9 Notes: 12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state. 13. Reset cycle is defined by the overlap of RS
Summary of the content on the page No. 6
CY7C150 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE vs.OUTPUT VOLTAGE vs.SUPPLY VOLTAGE 60 1.4 1.2 1.2 1.0 50 I I CC CC 1.0 0.8 40 0.8 V =5.0V CC 0.6 30 T =25°C A 0.6 0.4 20 V =5.0V 0.4 CC V =5.0V IN 0.2 10 0.2 I SB I SB 0 0.0 0.0 4.0 4.5 5.0 5.5 6.0 −55 25 125 0.0 1.0 2.0 3.0 4.0 AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V) SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME OUTPUT SINK CURRENT NORMALIZED ACCESS TIME vs.
Summary of the content on the page No. 7
CY7C150 Truth Table Inputs CS WE OE RS Outputs Mode H X X X High Z Not Selected L H X L High Z Reset L L X H High Z Write L H L H O −O Read 0 3 L X H H High Z Output Disable Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 10 CY7C150−10PC P13A 24-Lead (300-Mil) Molded DIP Commercial CY7C150−10SC S13 24-Lead Molded SOIC 12 CY7C150−12PC P13A 24-Lead (300-Mil) Molded DIP Commercial CY7C150−12SC S13 24-Lead Molded SOIC CY7C150−12DMB D14 24-Lead (300-Mil) CerD
Summary of the content on the page No. 8
CY7C150 MILITARY SPECIFICATIONS Switching Characteristics Group A Subgroup Testing Parameter Subgroups READ CYCLE DC Characteristics t 7, 8, 9, 10, 11 RC Parameter Subgroups t 7, 8, 9, 10, 11 AA V 1, 2, 3 OH t 7, 8, 9, 10, 11 OHA V 1, 2, 3 OL t 7, 8, 9, 10, 11 ACS V 1, 2, 3 IH WRITE CYCLE V Max. 1, 2, 3 IL t 7, 8, 9, 10, 11 WC I 1, 2, 3 IX t 7, 8, 9, 10, 11 SCS I 1, 2, 3 OZ t 7, 8, 9, 10, 11 AW I 1, 2, 3 CC t 7, 8, 9, 10, 11 HA t 7, 8, 9, 10, 11 SA t 7, 8, 9, 10, 11 PWE t 7, 8, 9, 10, 11 SD t
Summary of the content on the page No. 9
CY7C150 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 24-Lead (300-Mil) Molded DIP P13/P13A Document #: 38-05024 Rev. ** Page 9 of 11
Summary of the content on the page No. 10
CY7C150 Package Diagrams (continued) 24-Lead Molded SOIC S13 Document #: 38-05024 Rev. ** Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products fo
Summary of the content on the page No. 11
CY7C150 Document Title: Cy7C150 1K x4 Static RAM Document Number: 38-05024 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 106810 09/10/01 SZV Change from Spec number: 38-00028 to 38-05024 Document #: 38-05024 Rev. ** Page 11 of 11
