Summary of the content on the page No. 1
CY7C1354CV25
CY7C1356CV25
9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL™ Architecture
[1]
Features Functional Description
• Pin-compatible with and functionally equivalent to The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
ZBT™ 36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
• Supports 250-MHz bus operations with zero wait states
designed to support unlimited true back-to-back Read/Write
• Available speed grades are 250, 20
Summary of the content on the page No. 2
CY7C1354CV25 CY7C1356CV25 Logic Block Diagram–CY7C1356CV25 (512K x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U ADV/LD A T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BWa WRITE E DQs ARRAY S U CONTROL LOGIC G DRIVERS A F T DQPa I M E F BWb S DQPb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Contro
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CY7C1354CV25 CY7C1356CV25 Pin Configurations 100-pin TQFP Pinout DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V DDQ 4 V 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 SS 71 V V DDQ 11 DDQ V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC 14 V NC 14 V 67 SS CY7C1354CV25 67 SS V V DD 15 NC DD 15 NC 66 CY
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CY7C1354CV25 CY7C1356CV25 Pin Configurations (continued) 119-Ball BGA Pinout CY7C1354CV25 (256K × 36) 1 23 4 5 6 7 A V AA NC/18M A A V DDQ DDQ B NC/576M CE A ADV/LD ACE NC 2 3 C NC/1G A A V AA NC DD D DQ DQP V NC V DQP DQ c c SS SS b b DQ DQ V CE V DQ DQ E c c SS 1 SS b b F V DQ V V DQ V OE DDQ c SS SS b DDQ DQ DQ A DQ DQ G BW BW c c b b c b DQ DQ V DQ DQ H V c c SS WE b b SS V V NC V NC V V J DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ d d SS SS a a L DQ DQ NC DQ DQ BW BW d d a a d a M V DQ V V DQ
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CY7C1354CV25 CY7C1356CV25 Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1354CV25 (256K × 36) 1 2 3 4 567 89 10 11 A NC/576M A ADV/LD A A NC CE BW BW CE CEN 1 c b 3 B NC/1G A CE2 CLK WE OE NC/18M A NC BW BW d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS SS SS DDQ b DQ DQ V V V V V V V DQ DQ D c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ E c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ G c c DDQ DD SS SS
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CY7C1354CV25 CY7C1356CV25 Pin Definitions Pin Name I/O Type Pin Description A0 Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of A1 Synchronous the CLK. A BW BW Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. a, b, BW BW Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , c, d, a a a b b b BW controls DQ and DQP , BW controls DQ and DQP . c c c d d d WE In
Summary of the content on the page No. 7
CY7C1354CV25 CY7C1356CV25 Pin Definitions (continued) Pin Name I/O Type Pin Description NC – No connects. This pin is not connected to the die. NC (18, – These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 36, 72, 288M, 576M, and 1G densities. 144, 288, 576, 1G ZZ Input- ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition Asynchronous with data integrity preserved. For normal operation, this pin has to be LO
Summary of the content on the page No. 8
CY7C1354CV25 CY7C1356CV25 order to greatly simplify Read/Modify/Write sequences, which clock cycles are required to enter into or exit from this “sleep” can be reduced to simple Byte Write operations. mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not Because the CY7C1354CV25 and CY7C1356CV25 are considered valid nor is the completion of the operation common I/O devices, data should not be driven into the device guaranteed. The device
Summary of the content on the page No. 9
CY7C1354CV25 CY7C1356CV25 [2, 3, 4, 5, 6, 7, 8] Truth Table Address Operation Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H – SLEEP MODE None X H X X X X X X Tri-State [2, 3, 4, 9] Partial Write Cycle Description Function (CY7C1354CV25) BW BW BW BW WE d c b a Read H X X X X Write –No bytes written L H H H H Write Byte a– (DQ a
Summary of the content on the page No. 10
CY7C1354CV25 CY7C1356CV25 The ball is pulled up internally, resulting in a logic HIGH level. IEEE 1149.1 Serial Boundary Scan (JTAG) Test Data-In (TDI) The CY7C1354CV25/CY7C1356CV25 incorporates a serial boundary scan test access port (TAP) in the BGA package The TDI ball is used to serially input information into the only. The TQFP package does not offer this functionality. This registers and can be connected to the input of any of the part operates in accordance with IEEE Standard 1149.1-1900,
Summary of the content on the page No. 11
CY7C1354CV25 CY7C1356CV25 It is also loaded with the IDCODE instruction if the controller is SAMPLE Z placed in a reset state as described in the previous section. The SAMPLE Z instruction causes the boundary scan register When the TAP controller is in the Capture-IR state, the two to be connected between the TDI and TDO pins when the TAP least significant bits are loaded with a binary “01” pattern to controller is in a Shift-DR state. The SAMPLE Z command puts allow for fault isolation of the b
Summary of the content on the page No. 12
CY7C1354CV25 CY7C1356CV25 TAP Timing 123456 Test Clock (TCK) t t t TH TL CYC t t TMSS TMSH Test Mode Select (TMS) t t TDIS TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED [11, 12] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH Time 20 ns TH t TCK Clock LOW Time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Cl
Summary of the content on the page No. 13
CY7C1354CV25 CY7C1356CV25 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent 1.25V Input pulse levels ............................................... V to 2.5V SS Input rise and fall time .................................................... 1 ns 50Ω Input timing reference levels ........................................1.25V Output reference levels ................................................1.25V TDO Test load termination supply voltage.............................1.25V Z = 50Ω
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CY7C1354CV25 CY7C1356CV25 Boundary Scan Exit Order (256K × 36) (continued) Boundary Scan Exit Order (256K × 36) Bit # 119-ball ID 165-ball ID Bit # 119-ball ID 165-ball ID 48 M2 L1 1K4 B6 49 L1 K1 2H4 B7 50 K2 J1 3M4 A7 51 Not Bonded Not Bonded 4F4 B8 (Preset to 1) (Preset to 1) 5B4 A8 52 H1 G2 6G4 A9 53 G2 F2 7C3 B10 54 E2 E2 8B3 A10 55 D1 D2 9D6 C11 56 H2 G1 10 H7 E10 57 G1 F1 11 G6 F10 58 F2 E1 12 E6 G10 59 E1 D1 13 D7 D10 60 D2 C1 14 E7 D11 61 C2 B2 15 F6 E11 62 A2 A2 16 G7 F11 63 E4 A3 17
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CY7C1354CV25 CY7C1356CV25 Boundary Scan Exit Order (512K × 18) (continued) Boundary Scan Exit Order (512K × 18) Bit # 119-ball ID 165-ball ID Bit # 119-ball ID 165-ball ID 42 Not Bonded Not Bonded 1K4 B6 (Preset to 0) (Preset to 0) 2H4 B7 43 Not Bonded Not Bonded 3M4 A7 (Preset to 0) (Preset to 0) 4F4 B8 44 Not Bonded Not Bonded 5B4 A8 (Preset to 0) (Preset to 0) 6G4 A9 45 Not Bonded Not Bonded (Preset to 0) (Preset to 0) 7C3 B10 46 P2 N1 8B3 A10 47 N1 M1 9T2 A11 48 M2 L1 10 Not Bonded Not Bon
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CY7C1354CV25 CY7C1356CV25 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied...........
Summary of the content on the page No. 17
CY7C1354CV25 CY7C1356CV25 [16] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 555 pF IN A V = 2.5V, V = 2.5V DD DDQ C Clock Input Capacitance 5 5 5 pF CLK C Input/Output Capacitance 5 7 7 pF I/O [16] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameters Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 29.41 34.1 16.8 °C/W JA (Junction to test
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CY7C1354CV25 CY7C1356CV25 [18, 19] Switching Characteristics Over the Operating Range –250 –200 –166 Parameter Description Min. Max. Min. Max. Min. Max. Unit [17] t V (typical) to the First Access Read or Write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5 6 ns CYC F Maximum Operating Frequency 250 200 166 MHz MAX t Clock HIGH 1.8 2.0 2.4 ns CH t Clock LOW 1.8 2.0 2.4 ns CL Output Times t Data Output Valid after CLK Rise 2.8 3.2 3.5 ns CO t OE LOW to Output Valid 2.8 3.2 3.5 ns EOV t Data Out
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CY7C1354CV25 CY7C1356CV25 Switching Waveforms [23, 24, 25] Read/Write Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BWX A1 A2 A4 ADDRESS A3 A5 A6 A7 t CO t t DS DH t t t t DOH CLZ OEV CHZ t t AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) n-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: 23. For this w
Summary of the content on the page No. 20
CY7C1354CV25 CY7C1356CV25 Switching Waveforms (continued) [23, 24, 26] NOP, STALL and DESELECT CYCLES 123 456 789 10 CLK CEN CE ADV/LD WE BWX A1 A2 A3 A4 A5 ADDRESS t CHZ D(A4) D(A1) Q(A2) Q(A3) Q(A5) Data In-Out (DQ) WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED Note: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Document #:
