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CY7C1346H
2-Mbit (64K x 36) Pipelined Sync SRAM
[1]
Features Functional Description
• Registered inputs and outputs for pipelined operation The CY7C1346H SRAM integrates 64K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• 64K × 36 common I/O architecture
counter for internal burst operation. All synchronous inputs are
• 3.3V core power supply
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
• 3.3V/2
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CY7C1346H Selection Guide 166 MHz Unit Maximum Access Time 3.5 ns Maximum Operating Current 240 mA Maximum CMOS Standby Current 40 mA Pin Configuration 100-pin TQFP Pinout DQP c DQP 1 80 B DQ c 2 79 DQ B DQ C 3 78 DQ B V V DDQ 4 77 DDQ V SSQ 5 76 V SSQ DQ C DQ 6 75 B BYTE C DQ BYTE B C 7 74 DQ B DQ C 8 73 DQ B DQ C DQ 9 72 B V SSQ 10 71 V SSQ V DDQ 11 70 V DDQ DQ DQ C 12 69 B DQ C 13 68 DQ B NC V 14 67 SS V DD 15 66 NC CY7C1346H NC 16 65 V DD V SS ZZ 17 64 DQ D 18 63 DQ A DQ D 19 62 DQ A V DDQ
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CY7C1346H Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the 64K address locations. Sampled at the rising edge 0 1 Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A 1 2 3 1 0 feed the 2-bit counter. BW ,BW Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. A B BW ,BW Synchronous Sampled on the rising edge of CLK. C D GW Input- Global Write Enable I
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CY7C1346H Pin Definitions (continued) Name I/O Description V I/O Power Power supply for the I/O circuitry. DDQ Supply V I/O Ground Ground for the I/O circuitry. SSQ MODE Input- Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left DD Static floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. NC No Connects. Not internally connected to the die. 4M, 9M,18M,
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CY7C1346H Burst Sequences Interleaved Burst Address Table (MODE = Floating or V ) DD The CY7C1346H provides a two-bit wraparound counter, fed by A , A , that implements either an interleaved or linear burst First Second Third Fourth 1 0 sequence. The interleaved burst sequence is designed specif- Address Address Address Address ically to support Intel Pentium applications. The linear burst A , A A , A A , A A , A 1 0 1 0 1 0 1 0 sequence is designed to support processors that follow a 00 01 1
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CY7C1346H [2, 3, 4, 5, 6, 7] Truth Table Next Cycle Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselect Cycle, None H X X L X L X X X L-H Tri-State Power-down Deselect Cycle, None L L X L L X X X X L-H Tri-State Power-down Deselect Cycle, None L X H L L X X X X L-H Tri-State Power-down Deselect Cycle, None L L X L H L X X X L-H Tri-State Power-down Deselect Cycle, None L X H L H L X X X L-H Tri-State Power-down Sleep Mode, None X X X H X X X X X X Tri-State Power-down READ Cycle
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CY7C1346H [2, 3, 4, 5, 6, 7] Truth Table (continued) Next Cycle Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 WRITE Cycle, Current X X X L H H H L X L-H D Suspend Burst WRITE Cycle, Current H X X L X H H L X L-H D Suspend Burst [2, 3] Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – (DQ and DQP) H L HHH L A A Write Byte B – (DQ and DQP)H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP ) HL HL H H C C Wr
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CY7C1346H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current...................................................
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CY7C1346H [10] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [10] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test 30.32 °C/W JA (Junction to Ambient) methods and procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal R
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CY7C1346H [11, 12] Switching Characteristics Over the Operating Range -166 Parameter Description Min. Max. Unit [13] t V (Typical) to the First Access 1 ms POWER DD Clock t Clock Cycle Time 6.0 ns CYC t Clock HIGH 2.5 ns CH t Clock LOW 2.5 ns CL Output Times t Data Output Valid after CLK Rise 3.5 ns CO t Data Output Hold after CLK Rise 1.5 ns DOH [14, 15, 16] t Clock to Low-Z 0 ns CLZ [14, 15, 16] t Clock to High-Z 3.5 ns CHZ t OE LOW to Output Valid 3.5 ns OEV [14, 15, 16] t OE LOW to Output
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CY7C1346H Switching Waveforms [17] Read Cycle Timing t CYC CLK t t CL CH t t ADH ADS ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE, BW[A:D] Deselect t t CEH CES cycle CE t t ADVS ADVH ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Data Out (Q) Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) High-Z t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On
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CY7C1346H Switching Waveforms (continued) [17, 18] Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADH ADS t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when t t ADSP initiates burst WES WEH BWE, BW[A :D] t t WES WEH GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst OE t t DH DS Data In (D) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z D(A1) t OEHZ Data Out (Q) BURST READ Single
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CY7C1346H Switching Waveforms (continued) [17, 19, 20] Read/Write Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CES CEH CE ADV OE t t t CO DS DH t OELZ Data In (D) High-Z D(A3) D(A5) D(A6) t t OEHZ CLZ Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) High-Z Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unl
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CY7C1346H Switching Waveforms (continued) [21, 22] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05672 Rev. *B Page 14 of 16 [+] Feedback
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CY7C1346H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 166 CY7C1346H-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1346H-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial Package Diagrams 100-pin TQFP
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CY7C1346H Document History Page Document Title: CY7C1346H 2-Mbit (64K x 36) Pipelined Sync SRAM Document Number: 38-05672 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347357 See ECN PCI New Data sheet *A 420879 See ECN RXU Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 133MHz Speed bin. Changed three-state to tri-state. Modified test condition from V < V t
