Summary of the content on the page No. 1
CY7C1334H
2-Mbit (64K x 32) Pipelined SRAM with
NoBL™ Architecture
[1]
Features Functional Description
• Pin compatible and functionally equivalent to ZBT™ The CY7C1334H is a 3.3V/2.5V, 64K x 32
devices synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
• Internally self-timed output buffer control to eliminate
without the insertion of wait states. The CY7C1334H is
the need to use OE
equipped with the advanced No Bus Latency™ (NoB
Summary of the content on the page No. 2
CY7C1334H . Selection Guide 166 MHz 133 MHz Unit Maximum Access Time (t ) 3.5 4.0 ns CO Maximum Operating Current (I ) 240 225 mA DD Maximum CMOS Standby Current 40 40 mA Pin Configuration 100-Pin TQFP Pinout NC 1 80 NC 2 DQ 79 DQ C B 3 DQ 78 C DQ B V 4 77 DDQ V DDQ V 5 76 SSQ V SSQ DQ 6 C 75 DQ BYTE B BYTE C B 7 DQ C 74 DQ B 8 DQ C 73 DQ B 9 DQ 72 DQ C B 10 V 71 SSQ V SSQ V 11 70 DDQ V DDQ DQ 12 69 C DQ B CY7C1334H DQ 13 C 68 DQ B NC 14 67 V SS 15 V DD 66 NC NC 16 65 V DD 17 V ZZ 64 SS 18
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CY7C1334H Pin Definitions Name I/O Description A0, A1, A Input- Address Inputs used to select one of the 64K address locations. Sampled at the rising edge Synchronous of the CLK. A are fed to the two-bit burst counter. [1:0] BW Input- Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled [A:D] Synchronous on the rising edge of CLK. WE Input- Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. Synchronous This signal must
Summary of the content on the page No. 4
CY7C1334H the state of Chip Enables inputs or WE. WE is latched at the Functional Overview beginning of a burst cycle. Therefore, the type of access (Read The CY7C1334H is a synchronous-pipelined Burst SRAM or Write) is maintained throughout the burst sequence. designed specifically to eliminate wait states during Single Write Accesses Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The Write accesses are initiated when the
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CY7C1334H Linear Burst Address Table (MODE = GND) Interleaved Burst Address Table First Second Third Fourth (MODE = Floating or V ) DD Address Address Address Address A1, A0 A1, A0 A1, A0 A1, A0 First Second Third Fourth Address Address Address Address 00 01 10 11 A1, A0 A1, A0 A1, A0 A1, A0 01 10 11 00 00 01 10 11 10 11 00 01 01 00 11 10 11 00 01 10 10 11 00 01 11 10 01 00 [2, 3, 4, 5, 6, 7, 8] Cycle Description Truth Table Address Operation Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Deselect Cy
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CY7C1334H [2, 3] Write Cycle Description Function WE BW BW BW BW D C B A Read H X X X X Write − No bytes written L H H H H Write Byte A − (DQ) L HHH L A Write Byte B − (DQ)LHHLH B Write Bytes A, B L H H L L Write Byte C − (DQ)LHLHH C Write Bytes C,A L H L H L Write Bytes C, B L H L L H Write Bytes C, B, A L H L L L Write Byte D − (DQ)LLHHH D Write Bytes D, A L L H H L Write Bytes D, B L L H L H Write Bytes D, B, A L L H L L Write Bytes D, C L L L H H Write Bytes D, C, A L L L H L Write Bytes D
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CY7C1334H DC Input Voltage ....................................... −0.5V to V + 0.5V Maximum Rating DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-up Current.............................................
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CY7C1334H [11] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V, DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [11] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods and 30.32 °C/W JA (Junction to Ambient) procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resist
Summary of the content on the page No. 9
CY7C1334H [12, 13] Switching Characteristics Over the Operating Range 166 MHz 133 MHz Parameter Description Min. Max. Min. Max. Unit [14] t V (typical) to the First Access 11 ms POWER DD Clock t Clock Cycle Time 6.0 7.5 ns CYC t Clock HIGH 2.5 3.0 ns CH t Clock LOW 2.5 3.0 ns CL Output Times t Data Output Valid after CLK Rise 3.5 4.0 ns CO t Data Output Hold after CLK Rise 1.5 1.5 ns DOH [15, 16, 17] t Clock to Low-Z 00 ns CLZ [15, 16, 17] t Clock to High-Z 3.5 4.0 ns CHZ t OE LOW to Output Va
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CY7C1334H Switching Waveforms [18, 19, 20] Read/Write Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BW[A:D] A1 A2 A3 A4 A5 A6 A7 ADDRESS t CO t t t DS DH t t t DOH t t CLZ OEV CHZ AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: 18. For this waveform ZZ
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CY7C1334H Switching Waveforms (continued) [18, 19, 21] NOP, STALL, and Deselect Cycles 123 456 789 10 CLK CEN CE ADV/LD WE BW[A:D] A1 A2 A3 A4 A5 ADDRESS t CHZ D(A4) D(A1) Q(A2) Q(A3) Q(A5) Data In-Out (DQ) WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED [22, 23] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 21. The IGNOR
Summary of the content on the page No. 12
CY7C1334H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 166 CY7C1334H-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1334H-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 133 CY7C1334H-133AXC 51-85050 100-
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CY7C1334H Document History Page Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05678 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347357 See ECN PCI New Data Sheet *A 424820 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-State to Tri-State. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electri
