Summary of the content on the page No. 1
CY7C1330AV25
PRELIMINARY CY7C1332AV25
18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write
Features Functional Description
• Fast clock speed: 250, 200 MHz The CY7C1330AV25 and CY7C1332AV25 are high perfor-
mance, Synchronous Pipelined SRAMs designed with late
• Fast access time: 2.0, 2.25 ns
write operation. These SRAMs can achieve speeds up to 250
• Synchronous Pipelined Operation with Self-timed Late
MHz. Each memory cell consists of six transistors.
Write
Late write featur
Summary of the content on the page No. 2
CY7C1330AV25 CY7C1332AV25 PRELIMINARY Selection Guide CY7C1330AV25-250 CY7C1330AV25-200 CY7C1332AV25-250 CY7C1332AV25- 200 Unit Maximum Access Time 2.0 2.25 ns Maximum Operating Current 600 550 mA Maximum CMOS Standby Current 280 260 mA Pin Configurations 119-Ball BGA (14 x 22 x 2.4 mm) CY7C1330AV25 (512K x 36) 1 23 4 5 6 7 V AA NC A A V A DDQ DDQ NC AA NC A A NC B NC A A V AA NC C DD DQ DQ V ZQ V DQ DQ D c c SS SS b b E DQ DQ V CE V DQ DQ c c SS SS b b V DQ V OE V DQ V F DDQ c SS SS b DDQ G DQ
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Pin Definitions Name I/O Type Description A Input- Address Inputs used to select one of the address locations. Sampled at the rising Synchronous edge of the K. BWS Input- Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the a BWS Synchronous SRAM. Sampled on the rising edge of CLK. BWS controls DQ , BWS controls DQ , b a a b b BWS BWS controls DQ , BWS controls DQ . c c c d d BWS d WE Input- Write Enable Input, active LOW. Sam
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY A is loaded into the Address Register. The write signals are Introduction x latched into the Control Logic block. Functional Overview The data lines are automatically tri-stated regardless of the The CY7C1330AV25 and CY7C1332AV25 are synchronous- state of the OE input signal when a write is detected. This pipelined Late Write SRAMs running at speeds up to 250 MHz. allows the external logic to present the data on DQ and DQP All synchronous inputs pass thr
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY guaranteed. The device must be deselected prior to entering the “sleep” mode. CE must remain inactive for the duration of t after the ZZ input returns LOW. ZZREC [1, 2, 3, 4, 5] Cycle Description Truth Table Operation Address Used CE WE BWS CLK ZZ Comments x Deselected External 1 X X L-H 0 I/Os tri-state following next recognized clock. Begin Read External 0 1 X L-H 0 Address latched. Data driven out on the next rising edge of the clock. Begin Write External
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan test access register. This register is loaded when it is placed between the port (TAP) in the FBGA package. This port operates in accor- TDI and TDO pins as shown in TAP Controller Block Diagram. dance with IEEE Standard 1149.1-1900 but does not have the Upon power-up, the instruction r
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY EXTEST there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output EXTEST is a mandatory 1149.1 instruction which is to be will undergo a transition. The TAP may then try to capture a executed whenever the instruction register is loaded with all signal while in transition (metastable state). This will not harm 0s. EXTEST is not implemented in this SRAM TAP controller, the device, but there is no g
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY [6] TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document No: 001-07844 Rev. *A Page 8 of 19 [+] Feedback
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Selection TDI 2 1 0 TDO Circuitry Circuitry Instruction Register 31 30 29 . . 2 1 0 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS [7, 8, 9] TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = −2.0 mA 1.7 V OH1 OH V Output HIGH Voltage I = −100 µA2.1 V OH2 OH V Output LOW Vol
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY [10, 11] TAP AC Switching Characteristics Over the Operating Range (continued) Parameter Description Min. Max. Unit t Capture Hold after Clock Rise 5 ns CH Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX [11] TAP Timing and Test Conditions 1.25V ALL INPUT PULSES 2.5V 1.25V 50Ω 0V TDO Z = 50Ω 0 C = 20 pF L GND t t TH TL (a) Test Clock TCK t TCYC t TMSS t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Tes
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Scan Register Sizes Register Name Bit Size—CY7C1330AV25 Bit Size—CY7C1332AV25 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 70 51 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan reg
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Boundary Scan Order (512K x 36) Bit # Bump ID Bit # Bump ID Bit # Bump ID 15R 25 6F 49 2H 24P 26 7E 50 1H 34T 27 6E 51 3G 46R 28 7D 52 4D 55T 29 6D 53 4E 67T 30 6A 54 4G 76P 31 6C 55 4H 87P 32 5C 56 4M 96N 33 5A 57 3L 10 7N 34 6B 58 1K 11 6M 35 5B 59 2K 12 6L 36 3B 60 1L 13 7L 37 2B 61 2L 14 6K 38 3A 62 2M 15 7K 39 3C 63 1N 16 5L 40 2C 64 2N 17 4L 41 2A 65 1P 18 4K 42 2D 66 2P 19 4F 43 1D 67 3T 20 5G 44 2E 68 2R 21 7H 45 1E 69 4N 22 6H 46 2F 70 3R 23 7G 47 2
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY [7] DC Input Voltage ................................ –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... > 1500V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.......................
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY [17] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 2.5V DD C Clock Input Capacitance 6 pF CLK V = 1.5V DDQ C Input/Output Capacitance 7 pF I/O [17] Thermal Resistance Parameter Description Test Conditions BGA Typ. Unit Θ Thermal Resistance Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed 19.7 °C/W JA (Junction to Ambient) circuit board Θ Thermal Resistance 6.0 °C/W JC (Junction to
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY [18, 19, 20, 21] Switching Characteristics 250 200 Parameter Description Min. Max. Min. Max. Unit [22] t V (typical) to the First Access Read or Write11 ms Power CC Clock t Clock Cycle Time 4.0 5.0 ns CYC F Maximum Operating Frequency 250 200 MHz MAX t Clock HIGH 1.5 1.5 ns CH t Clock LOW 1.5 1.5 ns CL Output Times t Data Output Valid After CLK Rise 2.0 2.25 ns CO [17, 19, 21] t OE LOW to Output Valid 2.0 2.25 ns EOV t Data Output Hold After CLK Rise 0.5 0.5
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Switching Waveforms [23, 24, 25, 26] READ/WRITE/DESELECT Sequence (OE Controlled) K t t t CL CH CYC t t AS AH RA3 RA1 WA2 WA5 RA6 ADDRESS WA7 WA8 WE t t WES WEH BWS x t t WES WEH OE/ t EOHZ t EOLZ t t t EOV DS DH t t DOH DOH t t EOHZ CLZ Data Q1 D2 Q3 D5 Q6 D7 D8 In Out In/Out Out In In Out In Device t CHZ t t CO DH originally deselected t DS = DON’T CARE = UNDEFINED Notes: 23. The combination of WE and BWS (x = a, b, c, d for x36 and x = a, b for x18)
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Switching Waveforms (continued) READ/WRITE/DESELECT Sequence (CE Controlled) CLK t t CL t CH CYC t t CEH CES CE t t AH AS RA3 WA5 ADDRESS RA1 WA2 RA6 WA7 WA8 WE t t WES WEH BWS x t t WES WEH t t DS DH t t DOH DOH t CLZ Data Q1 D2 Q3 D5 Q6 D7 D8 In Out Out In In/Out Out In In Device t CHZ t CO originally deselected = DON’T CARE = UNDEFINED Document No: 001-07844 Rev. *A Page 17 of 19 [+] Feedback READ DESELECT WRITE READ Deselect WRITE READ DESELECT WRITE
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 250 CY7C1330AV25-250BGC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Commercial CY7C1332AV25-250BGC CY7C1330AV25-250BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 m
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CY7C1330AV25 CY7C1332AV25 PRELIMINARY Document History Page Document Title: CY7C1330AV25/CY7C1332AV25 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write SRAM Document Number: 001-07844 Orig. of REV. ECN No. Issue Date Change Description of Change ** 469811 See ECN NXR New data sheet *A 503690 See ECN VKN Minor change: Moved data sheet to web Document No: 001-07844 Rev. *A Page 19 of 19 [+] Feedback
