Summary of the content on the page No. 1
CY7C1329H
2-Mbit (64K x 32) Pipelined Sync SRAM
[1]
Features Functional Description
• Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• 64K × 32 common I/O architecture
counter for internal burst operation. All synchronous inputs are
• 3.3V core power supply
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
• 2.5V/3
Summary of the content on the page No. 2
CY7C1329H Selection Guide 166 MHz 133 MHz Unit Maximum Access Time 3.5 4.0 ns Maximum Operating Current 240 225 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100-pin TQFP Pinout NC 1 80 NC DQ C 2 79 DQ B DQ C DQ 3 78 B V DDQ 4 77 V DDQ V SSQ 5 76 V SSQ DQ C DQ 6 75 B DQ BYTE C BYTE B C 7 74 DQ B DQ C 8 73 DQ B DQ DQ C 9 72 B V SSQ 10 71 V SSQ V DDQ V 11 70 DDQ DQ C 12 69 DQ B DQ C 13 68 DQ B NC V 14 67 SS CY7C1329H V DD 15 66 NC NC 16 65 V DD V ZZ SS 17 64 DQ D 18 63 DQ A DQ D 19
Summary of the content on the page No. 3
CY7C1329H Pin Definitions Name I/O Description A , A , A Input- Address Inputs used to select one of the 64K address locations. Sampled at the rising edge 0 1 Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A 1 2 3 1 0 feed the 2-bit counter. BW ,BW , Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. A B Synchronous Sampled on the rising edge of CLK. BW , BW C D GW Input- Global Write Enab
Summary of the content on the page No. 4
CY7C1329H then the Write operation is controlled by BWE and BW Functional Overview [A:D] signals. The CY7C1329H provides Byte Write capability that All synchronous inputs pass through input registers controlled is described in the Write Cycle Descriptions table. Asserting by the rising edge of the clock. All data outputs pass through the Byte Write Enable input (BWE) with the selected Byte output registers controlled by the rising edge of the clock. Write (BW ) input, will selectively write to
Summary of the content on the page No. 5
CY7C1329H Interleaved Burst Address Table Linear Burst Address Table (MODE = GND) (MODE = Floating or V ) DD First Second Third Fourth Address Address Address Address First Second Third Fourth A , A A , A A , A A , A Address Address Address Address 1 0 1 0 1 0 1 0 A , A A , A A , A A , A 00 01 10 11 1 0 1 0 1 0 1 0 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I Sleep m
Summary of the content on the page No. 6
CY7C1329H [2, 3, 4, 5, 6, 7] Truth Table Next Cycle Add. Used Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE 1 2 3 Unselected None None H X X L X L X X X Unselected None None L L X L L X X X X Unselected None None L X H L L X X X X Unselected None None L L X L H L X X X Unselected None None L X H L H L X X X Begin Read External None X X X H X X X X X Begin Read External External L H L L L X X X L Continue Read Next External L H L L L X X X H Continue Read Next External L H L L H L X L X Continue
Summary of the content on the page No. 7
CY7C1329H [2, 3] Truth Table for Read/Write (continued) Function GW BWE BW BW BW BW D C B A Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H LLLL H Write All Bytes H LLLLL Write All Bytes L XXXXX Document #: 38-05673 Rev. *B Page 7 of 16 [+] Feedback
Summary of the content on the page No. 8
CY7C1329H DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage ......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current .................................................
Summary of the content on the page No. 9
CY7C1329H [10] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [10] Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test 30.32 °C/W JA (Junction to Ambient) methods and procedures for measuring thermal impedance, per Θ Thermal Resistance 6.85
Summary of the content on the page No. 10
CY7C1329H [11, 12] Switching Characteristics Over the Operating Range 166 MHz 133 MHz Parameter Description Min. Max Min. Max Unit [13] t V (Typical) to the First Access 11 ms POWER DD Clock t Clock Cycle Time 6.0 7.5 ns CYC t Clock HIGH 2.5 3.0 ns CH t Clock LOW 2.5 3.0 ns CL Output Times t Data Output Valid after CLK Rise 3.5 4.0 ns CO t Data Output Hold after CLK Rise 1.5 1.5 ns DOH [14, 15, 16] t Clock to Low-Z 00 ns CLZ [[14, 15, 16] t Clock to High-Z 3.5 4.0 ns CHZ t OE LOW to Output Val
Summary of the content on the page No. 11
CY7C1329H Switching Waveforms [17] Read Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE, BW[A:D] Deselect t t CES CEH cycle CE t t ADVS ADVH ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Data Out (Q) High-Z Q(A1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On
Summary of the content on the page No. 12
CY7C1329H Switching Waveforms (continued) [17, 18] Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADH ADS t t ADS ADH ADSC t t AH AS A1 A2 A3 ADDRESS Byte write signals are ignored for first cycle when t t ADSP initiates burst WES WEH BWE, BW[A :D] t t WES WEH GW t t CES CEH CE t t ADVH ADVS ADV ADV suspends burst OE t t DS DH Data In (D) D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z t OEHZ Data Out (Q) BURST READ Single
Summary of the content on the page No. 13
CY7C1329H Switching Waveforms (continued) [17, 19, 20] Read/Write Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW[A:D] t t CES CEH CE ADV OE t t t CO DS DH t OELZ Data In (D) High-Z D(A3) D(A5) D(A6) t t OEHZ CLZ Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) High-Z Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unl
Summary of the content on the page No. 14
CY7C1329H Switching Waveforms (continued) [21, 22] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05673 Rev. *B Page 14 of 16 [+] Feedback
Summary of the content on the page No. 15
CY7C1329H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 166 CY7C1329H-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1329H-166AXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 133 CY7C1329H-133AXC 100-pin Thin Quad Fl
Summary of the content on the page No. 16
CY7C1329H Document History Page Document Title: CY7C1329H 2-Mbit (64K x 32) Pipelined Sync SRAM Document Number: 38-05673 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 347357 See ECN PCI New Data Sheet *A 424820 See ECN RXU Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-State to Tri-State. Modified “Input Load” to “Input Leakage Current except ZZ and M
