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CY7C1345G
4-Mbit (128K x 36) Flow Through Sync SRAM
Features Functional Description
■ 128K x 36 common IO The CY7C1345G is a 128K x 36 synchronous cache RAM
designed to interface with high speed microprocessors with
■ 3.3V core power supply (V )
DD
minimum glue logic. The maximum access delay from clock rise
is 6.5 ns (133 MHz version). A two-bit on-chip counter captures
■ 2.5V or 3.3V IO supply (V )
DDQ
the first address in a burst and increments the address automat-
■ Fast clock-to-output time
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CY7C1345G Logic Block Diagram ADDRESS A0, A1, A REGISTER A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD, DQPD DQD, DQPD BYTE BW D BYTE BYTE WRITE REGISTER WRITE WRITE REGISTER REGISTER DQC, DQPC DQC, DQPC BYTE BW C BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQs MEMORY SENSE BUFFERS DQPA ARRAY DQB, DQPB AMPS DQB, DQPB DQPB BYTE BW B BYTE DQPC WRITE REGISTER WRITE REGISTER DQPD DQA, DQPA DQA, DQPA BYTE BW A BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 RE
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CY7C1345G Pin Configurations 100-Pin TQFP Pinout DQP 1 C 80 DQP B DQ 2 C 79 DQ B DQ 3 C 78 DQ B V 4 DDQ 77 V DDQ V 5 SSQ 76 V SSQ DQ 6 C 75 DQ B DQ 7 C 74 DQ B BYTE C DQ 8 C 73 DQ BYTE B B DQ 9 C 72 DQ B V 10 SSQ 71 V SSQ V 11 V DDQ 70 DDQ DQ 12 DQ C 69 B DQ 13 DQ C 68 B NC 14 67 V SS V 15 DD 66 NC CY7C1345G NC 16 65 V DD V 17 ZZ SS 64 DQ 18 D 63 DQ A DQ 19 D 62 DQ A V 20 DDQ 61 V DDQ V 21 SSQ 60 V SSQ DQ 22 D 59 DQ A BYTE D BYTE A DQ 23 D 58 DQ A DQ 24 DQ D 57 A DQ 25 DQ D 56 A V 26 V SSQ 55
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CY7C1345G Pin Configurations (continued) 119-Ball BGA Pinout 2 1 34 5 6 7 A V AA A A A V ADSP DDQ DDQ B NC/288M CE A ADSC A CE NC/576M 2 3 C NC/144M A A V A A NC/1G DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V V DQ DQ CE C C SS SS B B 1 V DQ V V DQ V F OE DDQ C SS SS B DDQ DQ DQ DQ DQ G BW BW ADV C C B B C B H DQ DQ V V DQ DQ C C SS GW SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D D A A A V DQ V V DQ V M BWE DDQ D SS SS A DDQ DQ DQ
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CY7C1345G Pin Definitions Name IO Description A0, A1, A Input Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A feed 1 2 3 [1:0] the two-bit counter. BW BW Input Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. A, B BW , BW Synchronous Sampled on the rising edge of CLK. C D GW Input Global Write Enable Input, Act
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CY7C1345G Pin Definitions (continued) Name IO Description MODE Input Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left DD Static floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. NC No Connects. Not Internally connected to the die. NC/9M, – No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/18M, NC/288M, NC/576M, a
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CY7C1345G Table 2. Linear Burst Address Table (MODE = GND) Burst Sequences The CY7C1345G provides an on-chip two-bit wrap around burst First Second Third Fourth counter inside the SRAM. The burst counter is fed by A and Address Address Address Address [1:0] follows either a linear or interleaved burst order. The burst order A , A A , A A , A A , A 1 0 1 0 1 0 1 0 is determined by the state of the MODE input. A LOW on MODE 00 01 10 11 selects a linear burst sequence. A HIGH on MODE selects an in
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CY7C1345G Truth Table [1, 2, 3, 4, 5] The truth table for CY7C1345G follows. Address Cycle Description CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Used Deselected Cycle, Power None H X X L X L X X X L-H Tri-State down Deselected Cycle, Power None L L X L L XXXX L-H Tri-State down Deselected Cycle, Power None L X H L L XXXX L-H Tri-State down Deselected Cycle, Power None L L X L H L X X X L-H Tri-State down Deselected Cycle, Power None X X X L H L X X X L-H Tri-State down Sleep Mode, Power
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CY7C1345G Truth Table for Read or Write [1, 6] The partial truth table for read or write follows. Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L H H H H Write Byte (A, DQP)HLHHHL A Write Byte (B, DQP)HLHHLH B Write Bytes (B, A, DQP , DQP)H L H H L L A B Write Byte (C, DQP)HLHLHH C Write Bytes (C, A, DQP , DQP)H L H L H L C A Write Bytes (C, B, DQP , DQP)H L H L L H C B Write Bytes (C, B, A, DQP , DQP , DQP) H L H LLL C B A Write Byte (D, DQP) H L L HHH D Write Bytes (D, A, DQP , DQP
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CY7C1345G DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may shorten the battery life of Static Discharge Voltage the device. These user guidelines are not tested. (MIL-STD-883, Method 3015) .................................. >2001V Storage Temperature ................................. –65°C to +150°C Latch up Current..................................
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CY7C1345G Capacitance Tested initially and after any design or process change that may affect these parameters. 100 TQFP 119 BGA Parameter Description Test Conditions Unit Max Max C Input Capacitance T = 25°C, f = 1 MHz, 55 pF IN A V = 3.3V. DD C Clock Input Capacitance 5 5 pF CLK V = 3.3V DDQ C Input or Output Capacitance 5 7 pF IO Thermal Resistance Tested initially and after any design or process change that may affect these parameters. 100 TQFP 119 BGA Parameter Description Test Conditions
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CY7C1345G Switching Characteristics [9, 10] Over the Operating Range –133 –100 Parameter Description Unit Min Max Min Max [11] t V (Typical) to the first Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 2.5 4.0 ns CH t Clock LOW 2.5 4.0 ns CL Output Times t Data Output Valid After CLK Rise 6.5 8.0 ns CDV t Data Output Hold After CLK Rise 2.0 2.0 ns DOH [12, 13, 14] t Clock to Low Z 00 ns CLZ [12, 13, 14] t Clock to High Z 3.5 3.5 ns CHZ t OE LOW to Output Valid 3.5 3.5
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CY7C1345G Timing Diagrams [15] Figure 1 shows the read cycle timing. Figure 1. Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 t t WES WEH GW, BWE,BW [A:B] Deselect Cycle t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst OE t t t CDV OEV OELZ t t OEHZ CHZ t DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Data Out (Q) Q(A1) High-Z t CDV Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED N
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CY7C1345G Timing Diagrams (continued) [15, 16] Figure 2 shows the write cycle timing. Figure 2. Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC extends burst t t ADS ADH t t ADS ADH ADSC t t AH AS A1 A2 A3 ADDRESS Byte write signals are ignored for first cycle when ADSP initiates burst t t WES WEH BWE, BW [A:B] t t WEH WES GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst OE t t DS DH Data in (D) High-Z D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
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CY7C1345G Timing Diagrams (continued) [16, 17, 18] Figure 3 shows the read and write timing. Figure 3. Read/Write Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WES WEH BWE, BW [A:B] t t CEH CES CE ADV OE t t DS DH t OELZ High-Z D(A3) D(A5) D(A6) Data In (D) t OEHZ t CDV Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back Back-to-Back READs Single WRITE BURST READ WRITEs DON’T CARE UNDEFINED Notes: 17. The data bus (Q) remains in high
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CY7C1345G Timing Diagrams (continued) [19, 20] Figure 4 shows the ZZ mode timing. Figure 4. ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 19. Device must be deselected when entering ZZ mode. See “Truth Table” on page 8 for all possible signal conditions to deselect the device. 20. DQs are in high-Z when exiting ZZ sleep mode. Document Number: 38-05517 Rev. *E Page 16 of 20
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CY7C1345G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating Part and Package Type (MHz) Ordering Code Diagram Range 133 CY7C1345G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1345G-133BGC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) CY7C1345G-133BGXC 119-Ball Grid Array (14 x 22 x 2.4 mm)
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CY7C1345G Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF NOTE: 0.05 MIN. 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. 0°-7
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CY7C1345G Package Diagrams (continued) Figure 6. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115 Ø0.05 M C Ø0.25MCAB A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 16 237 4 5 7 65 43 21 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U 1.27 0.70 REF. A 3.81 12.00 7.62 B 14.00±0.20 0.15(4X) 30° TYP. SEATING PLANE C 51-85115-*B Document Number: 38-05517 Rev. *E Page 19 of 20 0.25 C 0.56 0.90±0.05 60±0.10 19.50 2.40 MAX. 0.15 C 22.00±0.20 20.32 10.16 1.27
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CY7C1345G Document History Page Document Title: CY7C1345G, 4-Mbit (128K x 36) Flow Through Sync SRAM Document Number: 38-05517 Orig. of REV. ECN NO. Issue Date Description of Change Change See ECN ** 224365 RKF New datasheet See ECN *A 278513 VBL Deleted 66 MHz Changed TQFP package to Pb-free TQFP in Ordering Information section Added BG Pb-free package See ECN *B 333626 SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Packages as per JEDEC standards and updated the
