Summary of the content on the page No. 1
CY7C1019CV33
128K x 8 Static RAM
device has an automatic power-down feature that significantly
Features
reduces power consumption when deselected.
• Pin and function compatible with CY7C1019BV33
Writing to the device is accomplished by taking Chip Enable
•High speed (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O through I/O ) is then written into the location
0 7
—t = 10 ns
AA
specified on the address pins (A through A ).
0 16
• CMOS for optimum speed/power
Reading fr
Summary of the content on the page No. 2
CY7C1019CV33 [1] Pin Configuration 48-ball VFBGA (Top View) 1 2 3 4 5 6 A A OE A NC NC 2 6 7 A A A I/O NC CE I/O B 1 5 7 0 A A C I/O NC NC I/O 0 4 1 6 V NC A V NC NC SS CC D 3 V NC NC V NC E CC NC SS F A A I/O NC I/O I/O 2 14 11 4 5 A A I/O A G NC WE 15 12 8 3 A A A A NC 13 NC H 10 16 9 Selection Guide -10 -12 -15 Unit Maximum Access Time 10 12 15 ns Maximum Operating Current 80 75 70 mA Maximum Standby Current 5 5 5 mA Note: 1. NC pins are not connected on the die. Document #: 38-05130 Rev.
Summary of the content on the page No. 3
CY7C1019CV33 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage............................................ >2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current...................................................... >200 mA Storage Temperature .................................–65°C to +150°C Ambient Temperature with Operating Range Power Applied....
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CY7C1019CV33 [4] AC Test Loads and Waveforms High-Z characteristics: R 317 Ω ALL INPUT PULSES 3.0V R 317 Ω 3.3V 90% 90% 3.3V OUTPUT 10% 10% OUTPUT GND R2 30 pF R2 351 Ω 5 pF 351 Ω (b) Fall Time: 1 V/ns Rise Time: 1 V/ns (a) (c) [5] Switching Characteristics Over the Operating Range -10 -12 -15 Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 10 12 15 ns RC t Address to Data Valid 10 12 15 ns AA t Data Hold from Address Change 3 3 3 ns OHA t 10 12 15 ns
Summary of the content on the page No. 5
CY7C1019CV33 Switching Waveforms [11, 12] Read Cycle No. 1 t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [12, 13] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PD ICC t PU V CC 50% 50% SUPPLY ISB CURRENT [14, 15] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t SCE t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID Notes: 11. Device is continuously selected. OE, C
Summary of the content on the page No. 6
CY7C1019CV33 Switching Waveforms (continued) [14, 15] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t t SD HD DATA I/O DATA VALID IN NOTE 16 t HZOE [15] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 16 DATA I/O DATA VALID t t LZWE HZWE Truth Table I/O –I/O Mode Power CE OE WE 0 7 H X X High Z Power-Down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write Acti
Summary of the content on the page No. 7
CY7C1019CV33 Ordering Information Speed Package Operating (ns) Ordering Code Diagram Package Type Range 10 CY7C1019CV33-10VC 51-85033 32-pin 400-Mil Molded SOJ Commercial CY7C1019CV33-10ZXC 51-85095 32-pin TSOP II (Pb-Free) CY7C1019CV33-10ZXI 32-pin TSOP II (Pb-Free) Industrial 12 CY7C1019CV33-12VC 51-85033 32-pin 400-Mil Molded SOJ Commercial CY7C1019CV33-12ZC 51-85095 32-pin TSOP II CY7C1019CV33-12ZXC 32-pin TSOP II (Pb-Free) CY7C1019CV33-12VI 51-85033 32-pin 400-Mil Molded SOJ Industrial
Summary of the content on the page No. 8
CY7C1019CV33 Package Diagrams (continued) 32-pin TSOP II (51-85095) 51-85095-** Document #: 38-05130 Rev. *F Page 8 of 10 [+] Feedback
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CY7C1019CV33 Package Diagrams (continued) 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) 51-85150-*D SEATING PLANE C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05130 Rev. *F Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The inform
Summary of the content on the page No. 10
CY7C1019CV33 Document History Page Document Title: CY7C1019CV33 128K x 8 Static RAM Document Number: 38-05130 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 109245 12/16/01 HGK New Data Sheet *A 113431 04/10/02 NSL AC Test Loads split based on speed *B 115047 08/01/02 HGK Added TSOP II Package and I Temp. Improved I limits CC *C 119796 10/11/02 DFP Updated standby current from 5 nA to 5 mA *D 123030 12/17/02 DFP Updated Truth Table to reflect single Chip Enable option *E 419
