Summary of the content on the page No. 1
CY62128B
®
MoBL
1-Mbit (128K x 8) Static RAM
[1]
Features Functional Description
• Temperature Ranges The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
— Commercial: 0°C to 70°C
expansion is provided by an active LOW Chip Enable (CE ),
1
— Industrial: –40°C to 85°C
an active HIGH Chip Enable (CE ), an active LOW Output
2
Enable (OE), and three-state drivers. This device has an
— Automotive: –40°C to 125°C
automatic power-down feature that redu
Summary of the content on the page No. 2
CY62128B ® MoBL Product Portfolio Power Dissipation Operating, I Standby, I CC SB2 V Range (V) (mA) (µA) CC Speed [2] [2] [2] Product Min. Typ. Max. (ns) Typ. Max. Typ. Max. CY62128BLL Industrial 4.5 5.0 5.5 55 7.5 20 2.5 15 Industrial 70 6 15 2.5 15 Automotive 70 6 25 2.5 25 Pin Configurations Top View SOIC NC V 1 32 CC A 16 2 31 A 15 A 30 14 3 CE 2 A 12 4 29 WE 28 A 5 A 7 13 27 A 6 A 6 8 26 A 5 7 A 9 25 A 4 8 A 11 A 24 9 3 OE A 23 10 A 2 10 A 22 1 CE 11 1 I/O 21 A 12 7 0 I/O I/O 0 20 6 1
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CY62128B ® MoBL Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage........................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current..................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied.
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CY62128B ® MoBL [6] Thermal Resistance Parameter Description Test Conditions 32 SOIC 32 TSOP 32 STSOP 32 RTSOP Unit Θ Thermal Resistance Test conditions follow standard test 66.17 97.44 105.14 97.44 °C/W JA (Junction to Ambient) methods and procedures for measuring thermal impedance, per Θ Thermal Resistance 30.87 26.05 14.09 26.05 °C/W JC EIA / JESD51. (Junction to Case) [6] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 9pF IN A V = 5.0
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CY62128B ® MoBL [7] Switching Characteristics Over the Operating Range 62128B-55 62128B-70 Parameter Description Min. Max. Min. Max. Unit READ CYCLE t Read Cycle Time 55 70 ns RC t Address to Data Valid 55 70 ns AA t Data Hold from Address Change 5 5 ns OHA t CE LOW to Data Valid, CE HIGH to Data Valid 55 70 ns ACE 1 2 t OE LOW to Data Valid 20 35 ns DOE t OE LOW to Low Z 0 0 ns LZOE [7, 9] t OE HIGH to High Z 20 25 ns HZOE [9] t CE LOW to Low Z, CE HIGH to Low Z 55 ns LZCE 1 2 [8, 9] t CE HIG
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CY62128B ® MoBL Switching Waveforms (continued) [13, 14] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE 1 CE 2 t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PD I t PU CC V CC 50% 50% SUPPLY I CURRENT SB [15, 16] Write Cycle No. 1 (CE or CE Controlled) 1 2 t WC ADDRESS t SCE CE 1 t SA CE 2 t SCE t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID Notes: 14. Address valid prior to or coincident with CE transition LOW and CE transition HIGH. 1 2 15
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CY62128B ® MoBL Switching Waveforms (continued) [15, 16] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE 1 CE 2 t SCE t t AW HA t t SA PWE WE OE t SD t HD DATA I/O DATA VALID IN 17 NOTE t HZOE [15, 16] Write Cycle No.3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE 1 CE 2 t SCE t t AW HA t t SA PWE WE t t SD HD NOTE 17 DATAI/O DATA VALID t t LZWE HZWE Note: 17. During this period the I/Os are in the output state and input signals should not be applied. Document #:
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CY62128B ® MoBL Truth Table CE CE OE WE I/O –I/O Mode Power 1 2 0 7 H X X X High Z Power-down Standby (I ) SB X L X X High Z Power-down Standby (I ) SB LH L H Data Out Read Active (I ) CC L H X L Data In Write Active (I ) CC L H H H High Z Selected, Outputs Disabled Active (I ) CC Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 55 CY62128BLL-55SI S34 32-Lead 450-Mil SOIC Industrial CY62128BLL-55SXI S34 32-Lead 450-Mil SOIC (Pb-Free) Industrial CY62128BLL
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CY62128B ® MoBL Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.118[2.997] 0.111[2.819] MAX. 0.004[0.102] 0.047[1.193] 0.004[0.102] 0.063[1.600] 0.050[1.270] MIN. 0.023[0.584] BSC. 0.039[0.990] 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B 32-Lead Thin Small Outline Package Type I (8x20 mm) Z32 51-85056-*D Document #: 38-05300 Rev. *C Page 9 of 11
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CY62128B ® MoBL Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package (8x13.4 mm) ZA32 51-85094-*D 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05300 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility
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CY62128B ® MoBL Document History Page ® Document Title: CY62128B MoBL 1-Mbit (128K x 8) Static RAM Document Number: 38-05300 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 116566 06/20/02 DSG Changed from Spec number: 38-00524 to 38-05300 *A 126601 06/09/03 JUI Changed CE to CE and added CE ≤ 0.3V in Data Retention Characteristics table 1 2 Removed these part numbers from Ordering Information table: CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC, CY62128BLL-70ZAC, CY6
