Summary of the content on the page No. 1
STK17T88
32K x 8 AutoStore™ nvSRAM with
Real Time Clock
Features Description
■ nvSRAM Combined With Integrated Real-Time Clock The Cypress STK17T88 combines a 256 Kb nonvolatile static
Functions (RTC, Watchdog Timer, Clock Alarm, Power RAM (nvSRAM) with a full-featured real-time clock in a reliable,
Monitor) monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
■ Capacitor or Battery Backup for RTC
Quantum Trap storage element included with each memory cell.
■
Summary of the content on the page No. 2
STK17T88 Pin Configurations [1] Relative PCB Area Usage Figure 1. 48-Pin SSOP V CAP 1 48 VCC NC 2 47 NC A 14 3 46 HSB A12 4 45 W A7 5 44 A13 A A6 43 6 6 A A5 9 7 42 INT NC 41 8 A 4 40 A 9 11 NC 10 39 NC (TOP) NC 38 11 NC NC 37 12 NC V SS 13 36 V SS NC 35 NC 14 V RTCbat 34 V 15 RTCcap DQ DQ 0 16 33 6 A 3 32 G 17 A 2 31 A 18 10 A 1 19 30 E 29 DQ A0 20 7 DQ 28 DQ 1 21 5 DQ 2 DQ 22 27 4 X DQ 1 23 26 3 X V 2 24 CC 25 Pin Descriptions Pin Name IO Type Description A -A Input Address: The 15 address in
Summary of the content on the page No. 3
STK17T88 Absolute Maximum Ratings Note: Stresses greater than those listed under “Absolute Voltage on Input Relative to Ground.................–0.5V to 4.1V Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device Voltage on Input Relative to V ...........–0.5V to (V + 0.5V) SS CC at conditions above those indicated in the operational sections Voltage on DQ or HSB......................–0.5V to (V + 0.5V) 0-7 CC of this specif
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STK17T88 DC Characteristics (continued) (V = 2.7V-3.6V) CC Commercial Industrial Symbol Parameter Units Notes Min Max Min Max V Output Logic “1” 2.4 2.4 V I = – 2 mA OH OUT Voltage V Output Logic “0” 0.4 0.4 V I = 4 mA OL OUT Voltage T Operating Temper- 0 70 –40 85 °C A ature V Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10% CC V Storage Capacitance 17 57 17 57 µFBetween V pin and V , 5V rated. CAP CAP SS NV Nonvolatile STORE 200 200 K C operations DATA Data Retention 20 20 Years At 55°C R
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STK17T88 RTC DC Characteristics Commercial Industrial Symbol Parameter Units Notes Min Max Min Max IBAK RTC Backup Current — 300 — 350 nA From either VRTCcap or VRTCbat VRTCbat RTC Battery Pin 1.8 3.3 1.8 3.3 V Typical = 3.0 Volts during normal operation Voltage VRTCcap RTC Capacitor Pin 1.2 2.7 1.2 2.7 V Typical = 2.4 Volts during normal operation Voltage tOSCS RTC Oscillator time to — 10 — 10 sec At Minimum Temperature from Power up or start Enable —5—5 sec At 25°C from Power up or Enable Fig
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STK17T88 SRAM READ Cycles #1 and #2 Symbols STK17T88-25 STK17T88-45 NO. Parameter Units #1 #2 Alt. Min Max Min Max 1t t Chip Enable Access Time 25 45 ns ELQV ACS [3] [5] 2t t t Read Cycle Time 25 45 ns AVAV ELEH RC [4] [6] 3t t t Address Access Time 25 45 ns AVQV AVQV AA 4t t Output Enable to Data Valid 12 20 ns GLQV OE [4] 5t t t Output Hold after Address Change 3 3 ns AXQX AXQX OH 6t t Address Change or Chip Enable to 33 ns ELQX LZ Output Active 7t t Address Change or Chip Disable to 10 15 ns
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STK17T88 SRAM WRITE Cycles #1 and #2 Symbols STK17T88-25 STK17T88-45 NO. Parameter Units #1 #2 Alt. Min Max Min Max 12 t t t Write Cycle Time 25 45 ns AVAV AVAV WC 13 t t t Write Pulse Width 20 30 ns WLWH WLEH WP 14 t t t Chip Enable to End of Write 20 30 ns ELWH ELEH CW 15 t t t Data Set-up to End of Write 10 15 ns DVWH DVEH DW 16 t t t Data Hold after End of Write 0 0 ns WHDX EHDX DH 17 t t t Address Set-up to End of Write 20 30 ns AVWH AVEH AW 18 t t t Address Set-up to Start of Write 0 0 ns
Summary of the content on the page No. 8
STK17T88 AutoStore/Power Up RECALL Symbols STK17T88 NO. Parameter Units Notes Standard Alternate Min Max 22 t Power up RECALL Duration 40 ms 9 HRECALL 23 t t STORE Cycle Duration 12.5 ms 10, 11 STORE HLHZ 24 V Low Voltage Trigger Level 2.65 V SWITCH 25 V V Rise Time 150 µS CCRISE CC Figure 9. AutoStore Power Up RECALL 25 23 23 22 22 NOTE: Read and Write cycles will be ignored during STORE, RECALL and while V is below V CC SWITCH Notes 9. t starts from the time V rises above V HRECALL CC SWITCH
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STK17T88 Software-Controlled STORE/RECALL Cycle [12, 13] In the following table, the software controlled STORE and RECALL cycle parameters are listed. Symbols STK17T88-35 STK17T88-45 NO. Parameter Units Notes E Cont Alternate Min Max Min Max 26 t t STORE / RECALL Initiation Cycle Time 25 45 ns 13 AVAV RC 27 t t Address Set-up Time 0 0 ns AVEL AS 28 t t Clock Pulse Width 20 30 ns ELEH CW 29 t Address Hold Time 1 1 ns EHAX 30 t RECALL Duration 100 100 ms RECALL [13] Figure 10. Software Store/Rec
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STK17T88 Hardware STORE Cycle Symbols STK17T88 NO. Parameter Units Notes Standard Alternate Min Max 31 t t Hardware STORE to SRAM Disabled 1 70 µs14 DELAY HLQZ 32 t Hardware STORE Pulse Width 15 ns HLHX Figure 11. Hardware STORE Cycle 32 23 31 Soft Sequence Commands Symbols Parameter STK17T88 Units Notes NO. Standard Min Max 33 t Soft Sequence Processing Time 70 µs 15, 16 SS Figure 12. Soft Sequence Command 33 33 Notes 14. On a hardware STORE initiation, SRAM operation continues to be enabled
Summary of the content on the page No. 11
STK17T88 MODE Selection E W G A -A Mode I/O Power Notes 14 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active LH L 0x0E38 Read SRAM Output Data 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data Active 17,18, 19 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0FC0 Nonvolatile Store Output High Z I CC2 LH L 0x0E38 Read SRAM Output Data Active 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 17,18, 19 0
Summary of the content on the page No. 12
STK17T88 (activated by HSB), Software Store (activated by an address nvSRAM Operation sequence), and AutoStore (on power down). The STK17T88 nvSRAM is made up of two functional compo- AutoStore operation, a unique feature of Cypress QuanumTrap nents paired in the same physical cell. These are the SRAM technology that is a standard feature on the STK17T88. memory cell and a nonvolatile QuantumTrap™ cell. The SRAM During normal operation, the device draws current from V to CC memory cell operates
Summary of the content on the page No. 13
STK17T88 If the STK17T88 is in a WRITE mode (both E and W low) at Software STORE power up, after a RECALL, or after a STORE, the WRITE is Data can be transferred from the SRAM to the nonvolatile inhibited until a negative transition on E or W is detected. This memory by a software address sequence. The STK17T88 protects against inadvertent writes during power up or brown out software STORE cycle is initiated by executing sequential E conditions. controlled READ cycles from six specific address l
Summary of the content on the page No. 14
STK17T88 A capacitor has the obvious advantage of being more reliable Real Time Clock and not containing hazardous materials. The capacitor is recharged every time the power is turned on so that the real time The clock registers maintain time up to 9,999 years in clock continues to have the same backup time over years of one-second increments. The user can set the time to any operation calendar time and the clock automatically keeps track of days of the week and month, leap years, and century tr
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STK17T88 minute, have one second either shortened by 128 or lengthened The watchdog timer is a free-running-down counter that uses the by 256 oscillator cycles. 32Hz clock (31.25 ms) derived from the crystal oscillator. The watchdog timer function does not operate unless the oscillator is If a binary “1” is loaded into the register, only the first 2 minutes running. of the 64 minute cycle is modified; if a binary 6 is loaded, the first 12 are affected, and so on. Therefore each calibration step
Summary of the content on the page No. 16
STK17T88 Figure 15 is a functional diagram of the interrupt logic. High/Low (H/L). When set to a 1, the INT pin is active high and the driver mode is push-pull. The INT pin can drive high only Figure 15. Interrupt Block Diagram when V >V . When set to a 0, the INT pin is active low CC SWITCH WDF and the drive mode is open-drain. The active low (open drain) Watchdog output is maintained even when power is lost. Timer WIE Pulse/Level (P/L). When set to a 1, the INT pin is driven for V CC PF
Summary of the content on the page No. 17
STK17T88 RTC Register Map BCD Format Data Register Function / Range D7 D6 D5 D4 D3 D2 D1 D0 0x7FFF 10s Years Years Years: 00-99 0x7FFE 0 0 0 10s Months Months: 01-12 Months 0x7FFD 0 0 10s Day of Month Day of Month Day of Month: 01-31 0x7FFC 0 0 0 0 0 Day of Week Day of week: 01-07 0x7FFB 0 0 10s Hours Hours Hours: 00-23 0x7FFA 0 10s Minutes Minutes Minutes: 00-59 0x7FF9 0 10s Seconds Seconds Seconds: 00-59 0x7FF8 OSCEN 0Cal Calibration [00000] Calibration values* [0] Sign 0x7FF7 WDS WDW WDT Watc
Summary of the content on the page No. 18
STK17T88 Register Map Detail Real Time Clock – Years 0x7FFF D7 D6 D5 D4 D3 D2 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Real Time Clock – Months 0x7FFE D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10s Months Month Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper n
Summary of the content on the page No. 19
STK17T88 Register Map Detail (continued) WDW Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0). This allows the user to strobe the watchdog without disturbing the time-out value. Setting this bit to 0 allows bits 5-0 to be written. WDT Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range or time-out values is 31.25 ms (a se
Summary of the content on the page No. 20
STK17T88 Register Map Detail (continued) Flags 0x7FF0 D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R WDF Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up AF Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags register is read or on pow
