Summary of the content on the page No. 1
PRELIMINARY
CY14B104LA, CY14B104NA
4 Mbit (512K x 8/256K x 16) nvSRAM
Features Functional Description
■ 20 ns, 25 ns, and 45 ns access times The Cypress CY14B104LA/CY14B104NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
■ Internally organized as 512K x 8 (CY14B104LA) or 256K x 16
organized as 512K bytes of 8 bits each or 256K words of 16 bits
(CY14B104NA)
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s mo
Summary of the content on the page No. 2
PRELIMINARY CY14B104LA, CY14B104NA Pinouts Figure 1. Pin Diagram - 48 FBGA (x8) (x16) Top View Top View (not to scale) (not to scale) 1 2 4 5 3 6 1 4 2 3 5 6 A A A OE NC A A A BLE 0 2 A OE NC 1 NC 0 1 2 A DQ A A NC 8 BHE CE DQ B A A 3 4 NC CE NC B 0 3 4 C DQ A A DQ DQ A A C DQ DQ NC NC DQ 9 5 6 1 2 5 10 0 6 4 V A V A A DQ V A V SS DQ 7 CC D SS DQ 7 DQ CC D 17 3 17 5 11 1 V A V E V A V CC DQ V DQ SS DQ V DQ SS E CAP 16 CC 16 12 4 2 CAP 6 A A F A A F DQ DQ DQ DQ NC DQ 13 14 DQ NC 14 15 5 6 3 14
Summary of the content on the page No. 3
PRELIMINARY CY14B104LA, CY14B104NA Pinouts (continued) Figure 3. Pin Diagram - 54 Pin TSOP II (x16) NC 54 HSB 1 [5] [4] NC 53 NC 2 A 52 A 0 3 17 A 51 A 1 4 16 A 50 A 2 5 15 49 A 3 6 OE 48 A BHE 4 7 CE 47 8 BLE DQ 46 DQ 0 9 15 DQ 10 45 DQ 1 14 54 - TSOP II DQ 11 44 DQ 2 13 (x16) DQ 43 DQ 12 3 12 V 42 CC V 13 Top View SS V 41 SS V 14 CC (not to scale) 40 DQ DQ 4 15 11 DQ 39 DQ 5 16 10 38 DQ DQ 17 6 9 37 DQ DQ 18 7 8 36 WE V 19 CAP 35 A A 5 20 14 34 A A 6 21 13 33 A A 22 12 7 32 A A 23 11 8 31 A
Summary of the content on the page No. 4
PRELIMINARY CY14B104LA, CY14B104NA Characteristics on page 8 for the size of V . The voltage on Device Operation CAP the V pin is driven to V by a regulator on the chip. A pull CAP CC The CY14B104LA/CY14B104NA nvSRAM is made up of two up should be placed on WE to hold it inactive during power up. functional components paired in the same physical cell. They are This pull up is effective only if the WE signal is tri-state during a SRAM memory cell and a nonvolatile QuantumTrap cell. The power up.
Summary of the content on the page No. 5
PRELIMINARY CY14B104LA, CY14B104NA remains disabled until the HSB pin returns HIGH. Leave the HSB The software sequence may be clocked with CE controlled reads unconnected if it is not used. or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is Hardware RECALL (Power Up) disabled. HSB is driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary During power up or after any low
Summary of the content on the page No. 6
PRELIMINARY CY14B104LA, CY14B104NA Table 1. Mode Selection (continued) [7] [3] A - A Mode I/O Power CE WE OE, BHE, BLE 15 0 [8] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data [8] L H L 0x4E38 Read SRAM Output Data Active I CC2 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 N
Summary of the content on the page No. 7
PRELIMINARY CY14B104LA, CY14B104NA ■ Power up boot firmware routines should rewrite the nvSRAM Best Practices into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to nvSRAM products have been used effectively for over 15 years. again rewrite the nvSRAM into the desired state as a safeguard While ease-of-use is one of the product’s main system values, against events that might flip the bit inadvertently such as experience ga
Summary of the content on the page No. 8
PRELIMINARY CY14B104LA, CY14B104NA Transient Voltage (<20 ns) on Maximum Ratings Any Pin to Ground Potential................ ..–2.0V to V + 2.0V CC Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device. These user guidelines are not tested. Capability (T = 25°C)....................................................1.0W A Storage Temperature ..................................–65 °C to +150 °C Surface Mount Pb Soldering Temperature (3 Seconds)................
Summary of the content on the page No. 9
PRELIMINARY CY14B104LA, CY14B104NA Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operation 200 K C Capacitance [12] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [12] In the following table, the thermal resistance parameters are listed. Parameter Descr
Summary of the content on the page No. 10
PRELIMINARY CY14B104LA, CY14B104NA AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [13] t t Read Cycle Time 20 25 45 ns RC RC [14] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE [14] t t Output Hold After Address Change 3 3 3 ns OHA OH [12, 15] t t Chip Enable to Output Active 3 3 3 ns LZCE LZ [12, 15]
Summary of the content on the page No. 11
PRELIMINARY CY14B104LA, CY14B104NA [3, 13, 17] Figure 7. SRAM Read Cycle #2: CE and OE Controlled Address Address Valid t t HZCE RC t ACE CE t AA t t LZCE HZOE t DOE OE t t HZBE LZOE t DBE BHE, BLE t LZBE High Impedance Data Output Output Data Valid t PU t PD Active I Standby CC [3, 16, 17, 18] Figure 8. SRAM Write Cycle #1: WE Controlled t WC Address Address Valid t t SCE HA CE t BW BHE, BLE t AW t PWE WE t SA t t HD SD Data Input Input Data Valid t t LZWE HZWE High Impedance Data Output Pre
Summary of the content on the page No. 12
PRELIMINARY CY14B104LA, CY14B104NA [3, 16, 17, 18] Figure 9. SRAM Write Cycle #2: CE Controlled t WC Address Valid Address t t t SA SCE HA CE t BW BHE, BLE t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Output [3, 16, 17, 18] Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled t WC Address Address Valid t SCE CE t t t SA HA BW BHE, BLE t AW t PWE WE t t SD HD Data Input Input Data Valid High Impedance Data Output Document #: 001-49918 Rev. *A Page 12 of 23 [+] Feedback
Summary of the content on the page No. 13
PRELIMINARY CY14B104LA, CY14B104NA AutoStore/Power Up RECALL 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max [19] t Power Up RECALL Duration 20 20 20 ms HRECALL [20] t STORE Cycle Duration 8 8 8 ms STORE [21] t Time Allowed to Complete SRAM Cycle 20 25 25 ns DELAY V Low Voltage Trigger Level 2.65 2.65 2.65 V SWITCH t VCC Rise Time 150 150 150 μs VCCRISE [12] V HSB Output Driver Disable Voltage 1.9 1.9 1.9 V HDIS t HSB To Output Active Time 5 5 5 μs LZHSB t HSB High Activ
Summary of the content on the page No. 14
PRELIMINARY CY14B104LA, CY14B104NA Software Controlled STORE/RECALL Cycle [24, 25] In the following table, the software controlled STORE and RECALL cycle parameters are listed. 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t STORE/RECALL Initiation Cycle Time 20 25 45 ns RC t Address Setup Time 0 0 0 ns SA t Clock Pulse Width 152030 ns CW t Address Hold Time 0 0 0 ns HA t RECALL Duration 200 200 200 μs RECALL Switching Waveforms [25] Figure 12. CE and OE Controlled Soft
Summary of the content on the page No. 15
PRELIMINARY CY14B104LA, CY14B104NA Hardware STORE Cycle 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t HSB To Output Active Time when write latch not set 20 25 25 ns DHSB t Hardware STORE Pulse Width 15 15 15 ns PHSB [26, 27] t Soft Sequence Processing Time 100 100 100 μs SS Switching Waveforms [20] Figure 14. Hardware STORE Cycle Write latch set t PHSB HSB (IN) t STORE t t HHHD DELAY HSB (OUT) t LZHSB DQ (Data Out) RWI Write latch not set t PHSB HSB pin is driven hi
Summary of the content on the page No. 16
PRELIMINARY CY14B104LA, CY14B104NA Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration [2] CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ –DQ ); Read Active 0 7 L H H High Z Output Disabled Active L L X Data in (DQ –DQ ); Write Active 0 7 For x16 Configuration [3] [3] [2] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby L X X H H High-Z Output Disabled Active
Summary of the content on the page No. 17
PRELIMINARY CY14B104LA, CY14B104NA Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 20 CY14B104LA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104LA-ZS20XC 51-85087 44-pin TSOP II CY14B104LA-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104LA-ZS20XI 51-85087 44-pin TSOP II CY14B104LA-BA20XCT 51-85128 48-ball FBGA Commercial CY14B104LA-BA20XC 51-85128 48-ball FBGA CY14B104LA-BA20XIT 51-85128 48-ball FBGA Industrial CY14B104LA-BA20XI 51-85128 48-ball
Summary of the content on the page No. 18
PRELIMINARY CY14B104LA, CY14B104NA Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY14B104LA-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104LA-ZS45XC 51-85087 44-pin TSOP II CY14B104LA-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104LA-ZS45XI 51-85087 44-pin TSOP II CY14B104LA-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104LA-BA45XC 51-85128 48-ball FBGA CY14B104LA-BA45XIT 51-85128 48-ball FBGA Industrial CY14B104LA-BA45XI 51-8
Summary of the content on the page No. 19
PRELIMINARY CY14B104LA, CY14B104NA Part Numbering Nomenclature CY 14 B 104 L A -ZS P 20 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) X - Pb-Free Speed: I - Industrial (–40 to 85°C) Blank - SnPb 20 - 20 ns 25 - 25 ns 45 - 45 ns P - 54 Pin Package: Blank - 44 Pin/48 Ball BA - 48 FBGA ZS - TSOP II Die Revision: Blank - No Rev st Data Bus: A - 1 Rev L - x8 N - x16 Density: 104 - 4 Mb Voltage: B - 3.0V NVSRAM 14 - Auto Store + Software Store + Hardware Store Cy
Summary of the content on the page No. 20
PRELIMINARY CY14B104LA, CY14B104NA Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document #: 001-49918 Rev. *A Page 20 of 23 [+] Feedback 1.194 (0.047) 0.991 (0.039
